| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
99 return ShOp | (Imm << 3); in getSORegOpc()
|
| H A D | ARMMCCodeEmitter.cpp | 1280 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1281 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1318 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1320 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2646 ValueType Ty, SDNode ShOp>
2651 (Ty (ShOp (Ty DPR:$Vn),
2663 (Ty (ShOp (Ty DPR:$Vn),
2867 (Ty (ShOp (Ty DPR:$src1),
2880 (Ty (ShOp (Ty DPR:$src1),
3248 ValueType Ty, SDNode ShOp>
3269 ValueType Ty,SDNode ShOp>
3276 ValueType Ty,SDNode ShOp>
3534 v4i32, v2i32, ShOp>;
3834 mul, ShOp>;
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2486 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
2489 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
3560 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
3577 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
3586 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
3587 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
3588 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
3596 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
3617 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2156 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
2159 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
2162 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
2165 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
2168 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
2172 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
2173 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
2181 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
2183 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 1468 Value *ShOp; in foldICmpTruncConstant() local
1472 match(X, m_Shr(m_Value(ShOp), m_APInt(ShAmtC))) && in foldICmpTruncConstant()
1474 return TrueIfSigned ? new ICmpInst(ICmpInst::ICMP_SLT, ShOp, in foldICmpTruncConstant()
1476 : new ICmpInst(ICmpInst::ICMP_SGT, ShOp, in foldICmpTruncConstant()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5908 SDValue ShOp = N0.getOperand(1); in hoistLogicOpWithSameOpcodeHands() local
5909 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
5910 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
5913 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
5916 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
5921 ShOp = N0.getOperand(0); in hoistLogicOpWithSameOpcodeHands()
5922 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
5923 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
5926 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
5929 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 1386 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1388 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|