| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 181 /// Setcc
|
| H A D | LoongArchFloat64InstrInfo.td | 164 /// Setcc
|
| H A D | LoongArchInstrInfo.td | 1356 /// Setcc
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 563 bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask);
4796 bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, in tryVPTESTM() argument
4799 assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 && in tryVPTESTM()
4803 ISD::CondCode CC = cast<CondCodeSDNode>(Setcc.getOperand(2))->get(); in tryVPTESTM()
4807 SDValue SetccOp0 = Setcc.getOperand(0); in tryVPTESTM()
4808 SDValue SetccOp1 = Setcc.getOperand(1); in tryVPTESTM()
4895 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM()
|
| H A D | X86ScheduleBtVer2.td | 230 def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
|
| H A D | X86ScheduleBdVer2.td | 493 def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
|
| H A D | X86SchedSandyBridge.td | 179 def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
|
| H A D | X86SchedSkylakeClient.td | 167 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
|
| H A D | X86SchedBroadwell.td | 184 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
|
| H A D | X86SchedHaswell.td | 186 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
|
| H A D | X86SchedSkylakeServer.td | 168 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
|
| H A D | X86SchedIceLake.td | 175 def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc.
|
| H A D | X86ISelLowering.cpp | 43493 SDValue Setcc = DAG.getSetCC(DL, SetccVT, Movmsk, CmpC, CondCode); in combinePredicateReduction() local
43494 SDValue Zext = DAG.getZExtOrTrunc(Setcc, DL, ExtractVT); in combinePredicateReduction()
52637 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, N0->getOperand(0), in combineSext() local
52640 DCI.CombineTo(N, Setcc); in combineSext()
52644 N0.getValueType(), Setcc); in combineSext()
52853 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, N0->getOperand(0), in combineZext() local
52856 DCI.CombineTo(N, Setcc); in combineZext()
52860 N0.getValueType(), Setcc); in combineZext()
52915 SDValue Setcc = DAG.getSetCC(DL, OpVT, LHS, RHS, CC); in truncateAVX512SetCCNoBWI() local
52916 return DAG.getNode(ISD::TRUNCATE, DL, VT, Setcc); in truncateAVX512SetCCNoBWI()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14385 SDValue Setcc = Cond.getOperand(0); in tryDemorganOfBooleanCondition() local
14388 if (Setcc.getOpcode() != ISD::SETCC) in tryDemorganOfBooleanCondition()
14389 std::swap(Setcc, Xor); in tryDemorganOfBooleanCondition()
14391 if (Setcc.getOpcode() != ISD::SETCC || !Setcc.hasOneUse() || in tryDemorganOfBooleanCondition()
14410 EVT SetCCOpVT = Setcc.getOperand(0).getValueType(); in tryDemorganOfBooleanCondition()
14417 Setcc = DAG.getSetCC(SDLoc(Setcc), VT, Setcc.getOperand(0), in tryDemorganOfBooleanCondition()
14418 Setcc.getOperand(1), CCVal); in tryDemorganOfBooleanCondition()
14421 Setcc = DAG.getSetCC(SDLoc(Setcc), VT, Setcc.getOperand(1), in tryDemorganOfBooleanCondition()
14425 Setcc = DAG.getSetCC(SDLoc(Setcc), VT, in tryDemorganOfBooleanCondition()
14426 DAG.getConstant(0, SDLoc(Setcc), VT), in tryDemorganOfBooleanCondition()
[all …]
|
| H A D | RISCVInstrInfoD.td | 396 /// Setcc
|
| H A D | RISCVInstrInfoZfh.td | 352 /// Setcc
|
| H A D | RISCVInstrInfoF.td | 603 /// Setcc
|
| H A D | RISCVInstrInfo.td | 1325 /// Setcc
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6825 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ); in combineShiftAnd1ToBitTest() local
6826 return DAG.getZExtOrTrunc(Setcc, DL, And->getValueType(0)); in combineShiftAnd1ToBitTest()
|