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Searched refs:SetCC (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
H A DX86ISelLowering.cpp25733 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
25738 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
25744 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
31397 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerADDSUBO_CARRY()
45490 SDValue SetCC; in checkBoolTestSetCCCombine() local
45496 SetCC = Op2; in checkBoolTestSetCCCombine()
45498 SetCC = Op1; in checkBoolTestSetCCCombine()
45522 SetCC = SetCC.getOperand(OpIdx); in checkBoolTestSetCCCombine()
45525 SetCC = SetCC.getOperand(0); in checkBoolTestSetCCCombine()
45528 switch (SetCC.getOpcode()) { in checkBoolTestSetCCCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1261 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1262 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1272 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1274 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1280 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1309 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1312 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1315 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td1957 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1959 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1961 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1963 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1965 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1983 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1985 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1987 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1989 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1993 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
[all …]
H A DPPCInstrInfo.td3904 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3908 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
3912 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
3914 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
3917 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
3919 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
3921 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)),
3923 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
3925 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),
3927 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp675 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
677 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
678 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
702 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
705 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
706 SetCC.getOperand(1), in performSELECTCombine()
709 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
732 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
740 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
741 SetCC.getOperand(1), in performSELECTCombine()
[all …]
H A DMipsSEISelLowering.cpp977 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
979 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
983 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
984 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
H A DMipsInstrInfo.td1520 // SetCC
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPInstrInfo.td104 // SetCC (lhs, rhs, cc, mask, vl)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp17813 SDValue SetCC = N->getOperand(0); in performANDSETCCCombine() local
17825 if (SetCC.getOpcode() == ISD::SETCC && in performANDSETCCCombine()
20310 const SDValue SetCC = N->getOperand(0); in performSignExtendSetCCCombine() local
20312 const SDValue CCOp0 = SetCC.getOperand(0); in performSignExtendSetCCCombine()
22737 SDValue SetCC = N->getOperand(0); in trySwapVSelectOperands() local
22738 if (SetCC.getOpcode() != ISD::SETCC || !SetCC.hasOneUse()) in trySwapVSelectOperands()
22756 DAG.getSetCC(SDLoc(SetCC), SetCC.getValueType(), SetCC.getOperand(0), in trySwapVSelectOperands()
22784 SDValue SetCC = N->getOperand(0); in performVSelectCombine() local
22785 if (SetCC.getOpcode() == ISD::SETCC && in performVSelectCombine()
22787 SDValue CmpLHS = SetCC.getOperand(0); in performVSelectCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2644 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
9459 SDValue SetCC = in visitXOR() local
9462 CombineTo(N, SetCC); in visitXOR()
12870 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
12881 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
12882 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
13085 SDValue SetCC = VSel.getOperand(0); in matchVSelectOpSizesWithSetCC() local
13215 SDValue SetCC = N->getOperand(0); in foldExtendedSignBitTest() local
13217 !SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1) in foldExtendedSignBitTest()
13220 SDValue X = SetCC.getOperand(0); in foldExtendedSignBitTest()
[all …]
H A DLegalizeVectorOps.cpp930 SDValue SetCC = in Expand() local
933 Results.push_back(DAG.getSelect(SDLoc(Node), Node->getValueType(0), SetCC, in Expand()
H A DLegalizeIntegerTypes.cpp1253 SDValue SetCC; in PromoteIntRes_SETCC() local
1258 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers, N->getFlags()); in PromoteIntRes_SETCC()
1261 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1263 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1267 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
H A DTargetLowering.cpp10406 SDValue SetCC; in expandUADDSUBO() local
10413 SetCC = in expandUADDSUBO()
10418 SetCC = in expandUADDSUBO()
10423 SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO()
10425 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
10446 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
10447 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
H A DSelectionDAGBuilder.cpp7576 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, in visitIntrinsicCall() local
7578 setValue(&I, SetCC); in visitIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2178 SDValue SetCC = in LowerSETCC() local
2182 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
2183 return SetCC; in LowerSETCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4310 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
4312 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
4314 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4408 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerUADDSUBO_CARRY() local
4410 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerUADDSUBO_CARRY()
4412 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerUADDSUBO_CARRY()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5806 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
5809 return SetCC; in lowerICMPIntrinsic()
5810 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
5835 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic() local
5838 return SetCC; in lowerFCMPIntrinsic()
5839 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
6140 SDNode *SetCC = nullptr; in LowerBRCOND() local
6144 SetCC = Intr; in LowerBRCOND()
6145 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
6163 assert(!SetCC || in LowerBRCOND()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp3129 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
3134 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6520 SDValue SetCC = DAG.getSetCC( in LowerOperation() local
6522 return DAG.getLogicalNOT(DL, SetCC, VT); in LowerOperation()
9156 SDValue SetCC = DAG.getSetCC(DL, XLenVT, Vec, Zero, CC); in lowerVectorMaskVecReduction() local
9157 SetCC = DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), SetCC); in lowerVectorMaskVecReduction()
9160 return SetCC; in lowerVectorMaskVecReduction()
9168 return DAG.getNode(BaseOpc, DL, Op.getValueType(), SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13198 SDValue SetCC; in PerformSELECTCombine() local
13207 SetCC = N->getOperand(0); in PerformSELECTCombine()
13208 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
13209 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
13210 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()