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Searched refs:SecondReg (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2255 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2312 SecondReg = Op1->getOperand(0).getReg(); in CanFormLdStDWord()
2313 if (FirstReg == SecondReg) in CanFormLdStDWord()
2414 Register FirstReg, SecondReg; in RescheduleOps() local
2422 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2430 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2436 .addReg(SecondReg, RegState::Define) in RescheduleOps()
2450 .addReg(SecondReg) in RescheduleOps()
2467 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2468 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4413 unsigned SecondReg = Inst.getOperand(1).getReg(); in expandTrunc() local
4429 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4437 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
5355 unsigned SecondReg = nextReg(FirstReg); in expandLoadStoreDMacro() local
5357 if (!SecondReg) in expandLoadStoreDMacro()
5376 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
5378 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
5402 unsigned SecondReg = nextReg(FirstReg); in expandStoreDM1Macro() local
5404 if (!SecondReg) in expandStoreDM1Macro()
5420 std::swap(FirstReg, SecondReg); in expandStoreDM1Macro()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp7821 MCRegister SecondReg; in tryParseGPRSeqPair() local
7822 Res = tryParseScalarRegister(SecondReg); in tryParseGPRSeqPair()
7827 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || in tryParseGPRSeqPair()
7828 (isXReg && !XRegClass.contains(SecondReg)) || in tryParseGPRSeqPair()
7829 (isWReg && !WRegClass.contains(SecondReg))) in tryParseGPRSeqPair()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1615 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect() local
1632 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
H A DPPCISelLowering.cpp6927 const unsigned SecondReg = State.AllocateReg(PPC::R10); in CC_AIX() local
6928 assert(FirstReg && SecondReg && in CC_AIX()
6933 CCValAssign::getCustomReg(ValNo, ValVT, SecondReg, RegVT, LocInfo)); in CC_AIX()