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Searched refs:SchedRead (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td117 def ReadSFBJmp : SchedRead;
118 def ReadSFBALU : SchedRead;
121 def ReadJmp : SchedRead;
122 def ReadJalr : SchedRead;
123 def ReadCSR : SchedRead;
124 def ReadMemBase : SchedRead;
125 def ReadFMemBase : SchedRead;
126 def ReadStoreData : SchedRead;
127 def ReadFStoreData : SchedRead;
128 def ReadIALU : SchedRead;
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H A DRISCVScheduleZb.td54 def ReadRotateImm : SchedRead;
55 def ReadRotateImm32 : SchedRead;
56 def ReadRotateReg : SchedRead;
57 def ReadRotateReg32 : SchedRead;
58 def ReadCLZ : SchedRead;
59 def ReadCLZ32 : SchedRead;
60 def ReadCTZ : SchedRead;
61 def ReadCTZ32 : SchedRead;
62 def ReadCPOP : SchedRead;
63 def ReadCPOP32 : SchedRead;
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H A DRISCVScheduleV.td124 def name # "_" # mx : SchedRead;
513 def ReadVLDX : SchedRead;
514 def ReadVSTX : SchedRead;
520 def ReadVLDSX : SchedRead;
521 def ReadVSTSX : SchedRead;
707 def ReadVIMovVX : SchedRead;
708 def ReadVIMovXV : SchedRead;
709 def ReadVIMovXX : SchedRead;
711 def ReadVFMovVF : SchedRead;
712 def ReadVFMovFV : SchedRead;
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H A DRISCVInstrInfoZvk.td251 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
262 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
278 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
290 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
302 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
314 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
327 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
328 defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
350 defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
H A DRISCVInstrInfoV.td103 class SchedCommon<list<SchedWrite> writes, list<SchedRead> reads,
109 !cast<SchedRead>("ReadVMergeOp_" # mx),
110 !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" #sew));
128 !cast<SchedRead>(!if(sew, read #"_" #mx #"_E" #sew,
175 [!cast<SchedRead>(readV), !cast<SchedRead>(readV0)],
181 [!cast<SchedRead>("ReadVMov" # n # "V")]
193 [!cast<SchedRead>("ReadVSTEV_" # lmul), ReadVSTX], mx=lmul,
207 [!cast<SchedRead>("ReadVSTS" # eew # "V_" # emul), ReadVSTX, ReadVSTSX],
249 [!cast<SchedRead>("ReadVSTEV_" #emul), ReadVSTX], emul, eew, forceMasked
271 [!cast<SchedRead>("ReadVSTS" #eew #"V_" #emul),
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H A DRISCVSchedSiFive7.td178 class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
1205 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1207 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
35 def ReadID : SchedRead; // 32/64-bit Divide
38 def ReadIM : SchedRead; // 32/64-bit Multiply
39 def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
50 def ReadST : SchedRead; // Read the stored value.
51 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
88 def ReadVLD : SchedRead;
H A DAArch64SchedThunderX.td191 // Subtarget-specific SchedRead types.
H A DAArch64SchedA53.td149 // Subtarget-specific SchedRead types.
H A DAArch64SchedA55.td208 // Subtarget-specific SchedRead types.
H A DAArch64SchedCyclone.td865 // Unused SchedRead types
H A DAArch64SchedA510.td221 // Subtarget-specific SchedRead types.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td13 def P10BR_Read : SchedRead;
14 def P10DF_Read : SchedRead;
15 def P10DV_Read : SchedRead;
16 def P10DX_Read : SchedRead;
17 def P10F2_Read : SchedRead;
18 def P10FX_Read : SchedRead;
19 def P10LD_Read : SchedRead;
20 def P10MU_Read : SchedRead;
21 def P10PM_Read : SchedRead;
22 def P10ST_Read : SchedRead;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSchedule.td61 def ReadALU : SchedRead;
67 def ReadALUsr : SchedRead; // Some operands are read later.
79 def ReadMUL : SchedRead;
86 def ReadMAC : SchedRead;
118 def ReadFPMUL : SchedRead; // multiplier read
119 def ReadFPMAC : SchedRead; // accumulator read
H A DARMScheduleR52.td9 // This file defines the SchedRead/Write data for the ARM Cortex-R52 processor.
46 def R52Read_ISS : SchedRead;
47 def R52Read_EX1 : SchedRead;
48 def R52Read_EX2 : SchedRead;
49 def R52Read_WRI : SchedRead;
50 def R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe
51 def R52Read_F1 : SchedRead;
52 def R52Read_F2 : SchedRead;
H A DARMScheduleM4.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
H A DARMScheduleM7.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
H A DARMScheduleA57.td774 // def A57ReadVFMA : SchedRead;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td218 // listed for implicit def operands. SchedRead types may optionally
224 // single SchedWrite and single SchedRead in any order.
234 class SchedRead : SchedReadWrite;
338 // A processor may define a ReadAdvance associated with a SchedRead
350 SchedRead ReadType = read;
353 // Directly associate a new SchedRead type with a delay and optional
358 // Define SchedRead defaults. Reads seldom need special treatment.
359 def ReadDefault : SchedRead;
427 // A SchedReadVariant is a single SchedRead type that maps to a list
428 // of SchedRead types under the conditions defined by its predicates.
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td15 def ReadAfterLd : SchedRead;
16 def ReadAfterVecLd : SchedRead;
17 def ReadAfterVecXLd : SchedRead;
18 def ReadAfterVecYLd : SchedRead;
22 // This SchedRead describes a bypass delay caused by data being moved from the
24 def ReadInt2Fpu : SchedRead;
48 // The SchedRead to tag register operands than don't need to be ready
50 SchedRead ReadAfterFold;
54 multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
H A DX86InstrSSE.td859 SchedRead Int2Fpu = ReadDefault> {
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp120 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
928 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, in FindReadAdvance() argument
931 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
932 return SchedRead.TheDef; in FindReadAdvance()
936 for (Record *A : SchedRead.Aliases) { in FindReadAdvance()
959 || SchedRead.TheDef == RA->getValueAsDef("ReadType")) { in FindReadAdvance()
970 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") { in FindReadAdvance()
973 SchedRead.TheDef->getName()); in FindReadAdvance()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td35 def RegReadAdv : SchedRead;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td27 def MIVGPRRead : SchedRead;
28 def MIMFMARead : SchedRead;