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Searched refs:SchedClass (Results 1 – 20 of 20) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp59 unsigned SchedClass) const { in computeInstrLatency()
73 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
79 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
80 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
83 if (SchedClass) in computeInstrLatency()
125 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
126 SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
129 if (SchedClass) in getReciprocalThroughput()
136 MCSchedModel::getReciprocalThroughput(unsigned SchedClass, in getReciprocalThroughput() argument
139 const InstrStage *I = IID.beginStage(SchedClass); in getReciprocalThroughput()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepTimingClasses.h18 inline bool is_TC1(unsigned SchedClass) { in is_TC1() argument
19 switch (SchedClass) { in is_TC1()
67 inline bool is_TC2(unsigned SchedClass) { in is_TC2() argument
68 switch (SchedClass) { in is_TC2()
99 inline bool is_TC2early(unsigned SchedClass) { in is_TC2early() argument
100 switch (SchedClass) { in is_TC2early()
110 inline bool is_TC3x(unsigned SchedClass) { in is_TC3x() argument
111 switch (SchedClass) { in is_TC3x()
143 inline bool is_TC4x(unsigned SchedClass) { in is_TC4x() argument
144 switch (SchedClass) { in is_TC4x()
H A DHexagonInstrInfo.cpp2666 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1() local
2667 return is_TC1(SchedClass); in isTC1()
2671 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2() local
2672 return is_TC2(SchedClass); in isTC2()
2676 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early() local
2677 return is_TC2early(SchedClass); in isTC2Early()
2681 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC4x() local
2682 return is_TC4x(SchedClass); in isTC4x()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp123 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() local
124 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
134 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
135 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
311 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput() local
312 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
324 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput() local
326 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
329 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
H A DMachinePipeliner.cpp1070 unsigned SchedClass = Inst->getDesc().getSchedClass(); in minFuncUnits() local
1074 make_range(InstrItins->beginStage(SchedClass), in minFuncUnits()
1075 InstrItins->endStage(SchedClass))) { in minFuncUnits()
1087 STI->getSchedModel().getSchedClassDesc(SchedClass); in minFuncUnits()
1117 unsigned SchedClass = MI.getDesc().getSchedClass(); in calcCriticalResources() local
1120 make_range(InstrItins->beginStage(SchedClass), in calcCriticalResources()
1121 InstrItins->endStage(SchedClass))) { in calcCriticalResources()
1130 STI->getSchedModel().getSchedClassDesc(SchedClass); in calcCriticalResources()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
124 return SU->SchedClass; in getSchedClass()
H A DSystemZScheduleZ196.td103 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZEC12.td106 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ13.td122 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ16.td123 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ14.td122 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ15.td122 // resources that it needs. These will be combined into a SchedClass.
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h268 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
269 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
270 return SU->SchedClass; in getSchedClass()
H A DTargetSubtargetInfo.h144 virtual unsigned resolveSchedClass(unsigned SchedClass, in resolveSchedClass() argument
H A DScheduleDAG.h253 const MCSchedClassDesc *SchedClass = variable
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp435 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getCVIResources() local
436 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage; in getCVIResources()
442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources()
454 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits() local
455 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); in getUnits()
465 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots() local
471 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots()
472 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h209 unsigned short SchedClass; // enum identifying instr sched class variable
600 unsigned getSchedClass() const { return SchedClass; } in getSchedClass()
H A DMCSchedule.h381 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
H A DMCSubtargetInfo.h220 virtual unsigned resolveVariantSchedClass(unsigned SchedClass, in resolveVariantSchedClass() argument
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1413 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables() local
1414 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1415 if (SchedClass.Name.size() < 18) in EmitSchedClassTables()
1416 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()