Searched refs:SVEDataVector (Results 1 – 2 of 2) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 70 SVEDataVector, enumerator
1260 RK = RegKind::SVEDataVector; in isSVEVectorReg()
1306 if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector) in isSVEDataVectorRegOfWidth()
2682 case RegKind::SVEDataVector: in parseVectorKind()
2923 return Kind == RegKind::SVEDataVector ? RegNum : 0; in matchRegisterNameAlias()
2972 case RegKind::SVEDataVector: in getNumRegsForRegKind()
7139 RegisterKind = RegKind::SVEDataVector; in parseDirectiveReq()
7141 tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector); in parseDirectiveReq()
7856 tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector); in tryParseSVEDataVector()
7864 const auto &KindRes = parseVectorKind(Kind, RegKind::SVEDataVector); in tryParseSVEDataVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1166 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
1168 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
1265 "isTypedVectorListMultiple<RegKind::SVEDataVector, " # NumRegs # ", 0, "
1375 let PredicateMethod = "isTypedVectorListStrided<RegKind::SVEDataVector, "
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