| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 477 STRICT_FSETCCS, enumerator
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| H A D | SelectionDAG.h | 1216 return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 315 Op.getOpcode() == ISD::STRICT_FSETCCS) { in LegalizeOp()
1705 Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandSETCC()
1706 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandSETCC()
1826 Node->getOpcode() == ISD::STRICT_FSETCCS) { in ExpandStrictFPOp()
1855 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
1889 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
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| H A D | LegalizeDAG.cpp | 1059 case ISD::STRICT_FSETCCS: in LegalizeOp()
1067 : Opc == ISD::STRICT_FSETCCS ? 3 in LegalizeOp()
1073 : Opc == ISD::STRICT_FSETCCS ? 1 in LegalizeOp()
4018 case ISD::STRICT_FSETCCS: { in ExpandNode()
4021 Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode()
4022 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode()
4947 Node->getOpcode() == ISD::STRICT_FSETCCS) in PromoteNode()
5206 case ISD::STRICT_FSETCCS: { in PromoteNode()
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| H A D | SelectionDAGDumper.cpp | 297 case ISD::STRICT_FSETCCS: return "strict_fsetccs"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 940 case ISD::STRICT_FSETCCS: in SoftenFloatOperand()
1124 Chain, N->getOpcode() == ISD::STRICT_FSETCCS); in SoftenFloatOp_SETCC()
1909 case ISD::STRICT_FSETCCS: in ExpandFloatOperand()
2080 N->getOpcode() == ISD::STRICT_FSETCCS); in ExpandFloatOp_SETCC()
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| H A D | LegalizeVectorTypes.cpp | 4544 case ISD::STRICT_FSETCCS: in WidenVecRes_StrictFP()
5563 case ISD::STRICT_FSETCCS: in isSETCCOp()
6052 case ISD::STRICT_FSETCCS: Res = WidenVecOp_STRICT_FSETCC(N); break; in WidenVectorOperand()
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| H A D | SelectionDAGISel.cpp | 1200 case ISD::STRICT_FSETCCS: in DoInstructionSelection()
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| H A D | SelectionDAG.cpp | 3434 case ISD::STRICT_FSETCCS: { in computeKnownBits()
4530 case ISD::STRICT_FSETCCS: { in ComputeNumSignBits()
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| H A D | LegalizeIntegerTypes.cpp | 94 case ISD::STRICT_FSETCCS: in PromoteIntegerResult()
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| H A D | DAGCombiner.cpp | 1106 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
9455 case ISD::STRICT_FSETCCS: { in visitXOR()
9461 N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS); in visitXOR()
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| H A D | SelectionDAGBuilder.cpp | 7814 case ISD::STRICT_FSETCCS: { in visitConstrainedFPIntrinsic()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 515 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
516 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
517 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal); in PPCTargetLowering()
536 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
537 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
1288 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in PPCTargetLowering()
3627 Op->getOpcode() == ISD::STRICT_FSETCCS); in LowerSETCC()
11615 case ISD::STRICT_FSETCCS: in LowerOperation()
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| H A D | PPCISelDAGToDAG.cpp | 5471 case ISD::STRICT_FSETCCS: in Select()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 426 ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS}; in RISCVTargetLowering()
450 ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, in RISCVTargetLowering()
1002 setOperationAction({ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, in RISCVTargetLowering()
1320 ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS, ISD::STRICT_FTRUNC, in RISCVTargetLowering()
6620 case ISD::STRICT_FSETCCS: in LowerOperation()
10245 if (Opc == ISD::STRICT_FSETCCS) { in lowerVectorStrictFSetcc()
10251 SDValue Tmp1 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc()
10253 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, in lowerVectorStrictFSetcc()
10266 SDValue OEQ = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 151 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in SystemZTargetLowering()
591 setOperationAction(ISD::STRICT_FSETCCS, MVT::v2f64, Custom); in SystemZTargetLowering()
592 setOperationAction(ISD::STRICT_FSETCCS, MVT::v4f32, Custom); in SystemZTargetLowering()
6107 case ISD::STRICT_FSETCCS: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 178 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in LoongArchTargetLowering()
208 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in LoongArchTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 624 def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 449 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
655 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Promote); in X86TargetLowering()
1104 setOperationAction(ISD::STRICT_FSETCCS, MVT::v2f64, Custom); in X86TargetLowering()
1105 setOperationAction(ISD::STRICT_FSETCCS, MVT::v4f32, Custom); in X86TargetLowering()
1484 setOperationAction(ISD::STRICT_FSETCCS, MVT::v4f64, Custom); in X86TargetLowering()
2144 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
23068 Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC()
23083 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC()
23632 Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
23705 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 448 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); in AArch64TargetLowering()
449 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom); in AArch64TargetLowering()
450 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom); in AArch64TargetLowering()
510 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in AArch64TargetLowering()
1772 setOperationAction(ISD::STRICT_FSETCCS, VT, Expand); in addTypeForNEON()
6124 case ISD::STRICT_FSETCCS: in LowerOperation()
9375 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1494 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); in ARMTargetLowering()
1496 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom); in ARMTargetLowering()
1498 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom); in ARMTargetLowering()
10503 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerFSETCC()
10672 case ISD::STRICT_FSETCCS: return LowerFSETCC(Op, DAG); in LowerOperation()
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