Home
last modified time | relevance | path

Searched refs:ST1 (Results 1 – 20 of 20) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAsmAlias.td388 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
389 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
390 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
391 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
392 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
393 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
394 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
395 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
396 def : InstAlias<"fxch", (XCH_F ST1), 0>;
397 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
[all …]
H A DX86Instr3DNow.td78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
H A DX86InstrControl.td20 // ST1 arguments when returning values on the x87 stack.
H A DX86InstrMMX.td153 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
H A DX86RegisterInfo.td440 def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
H A DX86InstrCompiler.td467 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
487 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp208 {codeview::RegisterId::ST1, X86::ST1}, in initLLVMToSEHAndCVRegMapping()
217 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td993 …(instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))…
995 … (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>;
999 … (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1004 … (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
1013 … (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
H A DAArch64SchedKryoDetails.td1848 (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>;
1854 …(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$…
1860 (instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1866 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
1872 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
H A DAArch64InstrInfo.td3833 // We must use ST1 to store vectors in big-endian.
3847 // We must use ST1 to store vectors in big-endian.
3935 // We must use ST1 to store vectors in big-endian.
3962 // We must use ST1 to store vectors in big-endian.
4086 // We must use ST1 to store vectors in big-endian.
4112 // We must use ST1 to store vectors in big-endian.
7828 defm ST1 : SIMDSt1Multiple<"st1">;
8039 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
8056 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
8132 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
[all …]
H A DAArch64SchedA510.td1271 def : InstRW<[CortexA510VSt0], (instregex "^ST1[BHWD]_IMM$",
1278 def : InstRW<[CortexA510VSt0], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseV1.td1785 def : InstRW<[V1Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
1789 "^ST1[BWD]$",
H A DAArch64SchedNeoverseN2.td2184 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
2191 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BWD]$",
H A DAArch64SchedNeoverseV2.td2714 def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BHWD]_IMM$",
2721 def : InstRW<[V2Write_2cyc_1L01_1V01], (instregex "^ST1[BWD]$",
H A DAArch64InstrFormats.td10600 // ST1 instructions have extra "1d" variants.
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def125 CV_REGISTER(ST1, 129)
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp21199 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) { in visitSTORE() local
21201 ST1->isUnindexed() && ST1->isSimple()) { in visitSTORE()
21203 ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() && in visitSTORE()
21204 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
21210 if (OptLevel != CodeGenOptLevel::None && ST1->hasOneUse() && in visitSTORE()
21211 !ST1->getBasePtr().isUndef() && in visitSTORE()
21212 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
21218 ST1->getMemoryVT().isScalableVector()) { in visitSTORE()
21219 if (ST1->getBasePtr() == Ptr && in visitSTORE()
21222 CombineTo(ST1, ST1->getChain()); in visitSTORE()
[all …]
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td725 def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPl">;
H A Darm_sve.td2044 defm ST1 : MultiVecStore<"st1">;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1546 case 1: RegNo = X86::ST1; break; in ParseRegister()