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/freebsd-14.2/contrib/llvm-project/llvm/lib/Support/BLAKE3/
H A Dblake3_dispatch.c65 SSE2 = 1 << 0, enumerator
100 features |= SSE2; in get_cpu_features()
103 features |= SSE2; in get_cpu_features()
157 if (features & SSE2) { in blake3_compress_in_place()
186 if (features & SSE2) { in blake3_compress_xof()
227 if (features & SSE2) { in blake3_hash_many()
268 if (features & SSE2) { in blake3_simd_degree()
H A DREADME.md271 portable C, SSE2, SSE4.1, AVX2, and AVX-512.
/freebsd-14.2/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod36 =item bit #26 denoting SSE2 support;
65 disables high-performance SSE2 code present in the crypto library, while
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
68 executed on SSE2 capable CPU, but under control of OS that does not
H A DOPENSSL_instrument_bus.pod40 line' was introduced with the SSE2 extensions.
/freebsd-14.2/sys/contrib/openzfs/lib/libspl/include/sys/
H A Dsimd.h82 SSE2, enumerator
136 [SSE2] = {1U, 0U, 1U << 26, EDX },
210 CPUID_FEATURE_CHECK(sse2, SSE2);
/freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/
H A DX86.cpp456 .Case("+sse2", SSE2) in handleTargetFeatures()
461 HasFloat16 = SSELevel >= SSE2; in handleTargetFeatures()
472 HasBFloat16 = SSELevel >= SSE2; in handleTargetFeatures()
981 case SSE2: in getTargetDefines()
1002 case SSE2: in getTargetDefines()
1250 .Case("sse2", SSELevel >= SSE2) in hasFeature()
1677 if (SSELevel < SSE2) in validateOperandSize()
H A DX86.h61 SSE2, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Subtarget.h55 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
201 bool hasSSE2() const { return X86SSELevel >= SSE2; } in hasSSE2()
H A DX86InstrVecCompiler.td389 // movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
427 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
448 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
469 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
H A DX86InstrUtils.td596 // SSE2 Instruction Templates:
598 // SDI - SSE2 instructions with XD prefix.
599 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
600 // S2SI - SSE2 instructions with XS prefix.
601 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
602 // PDI - SSE2 instructions with PD prefix, packed double domain.
603 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
604 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
605 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
607 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
[all …]
H A DX86.td71 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
72 "Enable SSE2 instructions",
97 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
98 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
1592 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
1896 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
H A DX86InstrSSE.td1351 // SSE2 instructions with XS prefix
1606 // SSE2 packed instructions with XS prefix
1778 // SSE2 register conversion intrinsics
2244 // SSE2 - Packed Integer Logical Instructions
3563 // SSE2 - Packed Integer Logical Instructions
3868 // SSE2 - Packed Integer Unpack Instructions
3974 // SSE2 - Packed Integer Extract and Insert
4039 // SSE2 - Packed Mask Creation
4066 // SSE2 - Conditional Store
4098 // SSE2 - Move Doubleword/Quadword
[all …]
H A DX86CallingConv.td318 // SSE2.
839 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
990 // call and if SSE2 is available, are passed in SSE registers.
H A DX86InstrFPStack.td68 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
H A DX86ScheduleBtVer2.td834 // SSE2/AVX Store Selected Bytes of Double Quadword - (V)MASKMOVDQ
H A DX86RegisterInfo.td734 // Scalar SSE2 floating point registers.
/freebsd-14.2/sys/contrib/openzfs/config/
H A Dtoolchain-simd.m457 AC_MSG_CHECKING([whether host toolchain supports SSE2])
65 AC_DEFINE([HAVE_SSE2], 1, [Define if host toolchain supports SSE2])
H A Dhost-cpu-c-abi.m442 dnl MMX, SSE, SSE2, 3DNow! etc.) are not frequently used. If your
/freebsd-14.2/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h118 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
/freebsd-14.2/sys/x86/linux/
H A Dlinux_vdso_gettc_x86.inc113 [2] = { /* No SSE2 */
/freebsd-14.2/sys/contrib/libb2/
H A Dblake2-dispatch.c27 SSE2 = 1, enumerator
109 feature = SSE2; in get_cpu_features()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DX86TargetParser.def142 X86_FEATURE_COMPAT(SSE2, "sse2", 3)
/freebsd-14.2/sys/contrib/libsodium/
H A DChangeLog73 - SSE2 implementations of `crypto_verify_*()` have been added.
126 are twice as fast as the SSE2 implementations. The speed gain is
219 - An SSE2 optimized implementation of Poly1305 was added, and is
H A Dconfigure.ac378 AC_MSG_CHECKING(for SSE2 instructions set)
/freebsd-14.2/crypto/openssl/
H A DINSTALL.md866 Exclude SSE2 code paths from 32-bit x86 assembly modules.
868 Normally SSE2 extension is detected at run-time, but the decision whether or not
870 means that if you happen to run OS kernel which does not support SSE2 extension
874 disengage SSE2 code paths upon application start-up, but if you aim for wider

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