Searched refs:SRC0_ENABLE (Results 1 – 2 of 2) sorted by relevance
300 SRC0_ENABLE = 1 << ID_SRC0, enumerator304 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,
2376 .addImm(AMDGPU::VGPRIndexMode::SRC0_ENABLE); in expandPostRAPseudo()