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Searched refs:SPLAT_VECTOR (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp136 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
137 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
152 setOperationAction(ISD::SPLAT_VECTOR, MVT::f16, Custom); in initializeHVXLowering()
206 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
1502 SDValue True = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in extendHvxVectorPred()
1880 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1882 SDValue VecW = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1884 SDValue VecN1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
3188 case ISD::SPLAT_VECTOR: in LowerHvxOperation()
3614 if (Ops[0].getOpcode() == ISD::SPLAT_VECTOR) { in PerformHvxDAGCombine()
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H A DHexagonISelLowering.cpp1646 ISD::SPLAT_VECTOR, in HexagonTargetLowering()
1705 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); in HexagonTargetLowering()
2367 case ISD::SPLAT_VECTOR: in getSplatValue()
2565 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector32()
2628 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector64()
2872 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h627 SPLAT_VECTOR, enumerator
H A DSelectionDAG.h869 return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
H A DTargetLowering.h4077 return Op.getOpcode() == ISD::SPLAT_VECTOR || in isTargetCanonicalConstantNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp144 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
363 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicateImpl()
401 LHS.getOpcode() != ISD::SPLAT_VECTOR)) in matchBinaryPredicate()
2719 case ISD::SPLAT_VECTOR: in isSplatValue()
2933 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
3096 case ISD::SPLAT_VECTOR: { in computeKnownBits()
4216 if (Val.getOpcode() == ISD::SPLAT_VECTOR) in isKnownToBeAPowerOfTwo()
4304 case ISD::SPLAT_VECTOR: { in ComputeNumSignBits()
6804 ISD::SPLAT_VECTOR, DL, VT, in getNode()
11659 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstOrConstSplat()
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H A DSelectionDAGDumper.cpp311 case ISD::SPLAT_VECTOR: return "splat_vector"; in getOperationName()
H A DLegalizeVectorOps.cpp1175 : ISD::SPLAT_VECTOR, in ExpandSELECT()
1522 !TLI.isOperationLegalOrCustom(ISD::SPLAT_VECTOR, EVLVecVT)))) in ExpandVP_MERGE()
H A DDAGCombiner.cpp10346 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
12312 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
12368 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
12370 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
14806 if (N0.getOpcode() == ISD::SPLAT_VECTOR && in visitTRUNCATE()
22238 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
23465 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); in visitBUILD_VECTOR()
24428 if (V.getOpcode() == ISD::SPLAT_VECTOR) in visitEXTRACT_SUBVECTOR()
26155 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) in visitINSERT_SUBVECTOR()
26639 N1.getOpcode() == ISD::SPLAT_VECTOR; in scalarizeBinOpOfSplats()
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H A DLegalizeVectorTypes.cpp1008 case ISD::SPLAT_VECTOR: in SplitVectorResult()
1863 StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi); in SplitVecRes_STEP_VECTOR()
1878 assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode"); in SplitVecRes_ScalarOp()
4085 case ISD::SPLAT_VECTOR: in WidenVectorResult()
H A DTargetLowering.cpp1167 case ISD::SPLAT_VECTOR: { in SimplifyDemandedBits()
6060 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactSDIV()
6232 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildSDIV()
6415 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildUDIV()
6702 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareUREMEqFold()
6961 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareSREMEqFold()
H A DLegalizeIntegerTypes.cpp134 case ISD::SPLAT_VECTOR: in PromoteIntegerResult()
1789 case ISD::SPLAT_VECTOR: in PromoteIntegerOperand()
5104 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break; in ExpandIntegerOperand()
H A DLegalizeDAG.cpp4196 case ISD::SPLAT_VECTOR: in ExpandNode()
5573 case ISD::SPLAT_VECTOR: { in PromoteNode()
H A DSelectionDAGBuilder.cpp3829 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1287 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1312 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1455 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1527 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1915 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in addTypeForFixedLengthSVE()
6220 case ISD::SPLAT_VECTOR: in LowerOperation()
13668 Op.getOpcode() != ISD::SPLAT_VECTOR && in isPow2Splat()
17708 if (Dup.getOpcode() != ISD::SPLAT_VECTOR) in performSVEAndCombine()
18383 if (V.getOpcode() == ISD::SPLAT_VECTOR) in performExtractSubvectorCombine()
19782 Comparator.getOpcode() == ISD::SPLAT_VECTOR) { in tryConvertSVEWideCompare()
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H A DAArch64ISelDAGToDAG.cpp213 case ISD::SPLAT_VECTOR: { in SelectDupZeroOrUndef()
231 case ISD::SPLAT_VECTOR: { in SelectDupZero()
247 case ISD::SPLAT_VECTOR: { in SelectDupNegativeZero()
282 if (N->getOpcode() != ISD::SPLAT_VECTOR) in SelectSVEShiftSplatImmR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp886 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT}, in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp721 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
788 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
936 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1042 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
1164 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1260 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
1402 ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR, in RISCVTargetLowering()
6420 case ISD::SPLAT_VECTOR: in LowerOperation()
6430 ISD::SPLAT_VECTOR, DL, in LowerOperation()
15888 case ISD::SPLAT_VECTOR: { in PerformDAGCombine()
H A DRISCVISelDAGToDAG.cpp61 case ISD::SPLAT_VECTOR: { in PreprocessISelDAG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp207 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in WebAssemblyTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td737 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5190 if (N->getOpcode() == ISD::SPLAT_VECTOR) in isZeroVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp28097 Op->getOpcode() == ISD::SPLAT_VECTOR) { in LowerFMINIMUM_FMAXIMUM()