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Searched refs:SMLAL (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h266 SMLAL, // 64bit Signed Accumulate Multiply enumerator
H A DARMInstrInfo.td4426 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4458 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4611 // Halfword multiply accumulate long: SMLAL<x><y>.
4612 class SMLAL<bits<2> opc1, string asm>
4621 def SMLALBB : SMLAL<0b00, "smlalbb">;
4622 def SMLALBT : SMLAL<0b10, "smlalbt">;
4623 def SMLALTB : SMLAL<0b01, "smlaltb">;
4624 def SMLALTT : SMLAL<0b11, "smlaltt">;
6435 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6446 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DARMScheduleR52.td279 "SMLAL", "UMLAL", "SMLALBT",
H A DARMScheduleSwift.td307 (instregex "SMLAL", "UMLAL", "SMLALBT",
H A DARMISelDAGToDAG.cpp3953 case ARMISD::SMLAL:{ in Select()
3967 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
H A DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
H A DARMISelLowering.cpp1833 MAKE_CASE(ARMISD::SMLAL) in getTargetNodeName()
12873 SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in AddCombineTo64BitSMLAL16() local
12876 SDValue HiMLALResult(SMLAL.getNode(), 1); in AddCombineTo64BitSMLAL16()
12877 SDValue LoMLALResult(SMLAL.getNode(), 0); in AddCombineTo64BitSMLAL16()
12966 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
13016 FinalOpc == ARMISD::SMLAL && !AddeSubeNode->hasAnyUseOfValue(1) && in AddCombineTo64bitMLAL()
H A DARMInstrFormats.td1012 // SMLAL*
H A DARMInstrThumb2.td3228 // Halfword multiple accumulate long: SMLAL<x><y>
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td529 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
H A DAArch64InstrInfo.td5841 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
7318 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_sme.td461 // FMLAL/FMLSL/UMLAL/SMLAL
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8325 case ARM::SMLAL: in validateInstruction()