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Searched refs:SLLI (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMacroFusion.td36 "Enable SLLI+SRLI to be fused to zero extension of halfword",
38 CheckOpcode<[SLLI]>,
53 "Enable SLLI+SRLI to be fused to zero extension of word",
55 CheckOpcode<[SLLI]>,
71 "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
73 CheckOpcode<[SLLI]>,
H A DRISCVISelDAGToDAG.cpp228 SDValue SLLI = SDValue( in selectImm() local
677 SDNode *SLLI = in tryShrinkShlLogicImm() local
680 ReplaceNode(Node, SLLI); in tryShrinkShlLogicImm()
997 ReplaceNode(Node, SLLI); in Select()
1026 ReplaceNode(Node, SLLI); in Select()
1067 SDNode *SLLI = in Select() local
1101 SDNode *SLLI = in Select() local
1282 ReplaceNode(Node, SLLI); in Select()
1407 SDNode *SLLI = in Select() local
2974 case RISCV::SLLI: in hasAllNBitUsers()
[all …]
H A DRISCVOptWInstrs.cpp207 case RISCV::SLLI: in hasAllNBitUsers()
577 case RISCV::SLLI: in isSignExtendedW()
612 case RISCV::SLLI: in getWOp()
690 case RISCV::SLLIW: Opc = RISCV::SLLI; break; in stripWSuffixes()
H A DRISCVInstrInfoM.td115 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
H A DRISCVRegisterInfo.cpp325 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVSPILL()
402 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVRELOAD()
808 case RISCV::SLLI: in getRegAllocationHints()
H A DRISCVInstrInfo.td658 def SLLI : Shift_ri<0b00000, 0b001, "slli">;
1021 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1244 def : PatGprUimmLog2XLen<shl, SLLI>;
1260 (SRAI (SLLI $rs, (ImmSubFromXLen (XLenVT 1))),
1265 (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
1267 (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
1911 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>;
1916 (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
2121 (SRLI (SLLI $rs, (i64 (XLenSubTrailingOnes $mask))),
2129 def : Pat<(zext GPR:$src), (SRLI (SLLI GPR:$src, 32), 32)>;
[all …]
H A DRISCVInstrInfoXTHead.td575 (SLLI (TH_ADDSL GPR:$r, GPR:$r, 1),
578 (SLLI (TH_ADDSL GPR:$r, GPR:$r, 2),
581 (SLLI (TH_ADDSL GPR:$r, GPR:$r, 3),
608 (SLLI (TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 2),
636 (TH_FF0 (SLLI (XORI i64:$rs1, -1), 32))>;
H A DRISCVInstrInfo.cpp1334 case RISCV::SLLI: return RISCV::PseudoCCSLLI; break; in getPredicatedOpcode()
3078 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in getVLENFactoredAmount()
3102 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in getVLENFactoredAmount()
3113 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
3124 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
3149 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in getVLENFactoredAmount()
H A DRISCVInstrInfoZb.td715 (SLLI (SH1ADD GPR:$r, GPR:$r),
718 (SLLI (SH2ADD GPR:$r, GPR:$r),
721 (SLLI (SH3ADD GPR:$r, GPR:$r),
H A DRISCVExpandPseudoInsts.cpp218 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break; in expandCCOp()
H A DRISCVAsmPrinter.cpp598 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8), in EmitHwasanMemaccessSymbols()
H A DRISCVFrameLowering.cpp680 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
H A DRISCVInstrInfoC.td971 def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp24 case RISCV::SLLI: in getInstSeqCost()
147 unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI; in generateInstSeqImpl()
245 TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros); in generateInstSeq()
506 case RISCV::SLLI: in getOpndKind()
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h142 R_SHAMT_TYPE_INST(SLLI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
H A DRISCVCInstructions.h233 return SLLI{rd, rd, uint8_t(shamt)}; in DecodeC_SLLI()
H A DEmulateInstructionRISCV.cpp443 {"SLLI", 0xF800707F, 0x1013, DecodeRShamtType<SLLI>},
862 bool operator()(SLLI inst) { in operator ()()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp359 .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) in selectSHXADD_UWOp()
632 MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {MI.getOperand(2)}) in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td166 def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td441 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
H A DMipsScheduleGeneric.td1562 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3252 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td532 // Check if (mul r, imm) can be optimized to (SLLI (ALSL r, r, i0), i1),