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Searched refs:SETULT (Results 1 – 25 of 58) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td189 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
198 def : PatFPSetcc<SETULT, FCMP_CULT_S, FPR32>;
218 defm : PatFPBrcond<SETULT, FCMP_CULT_S, FPR32>;
235 def : PatStrictFsetccs<SETULT, FCMP_SULT_S, FPR32>;
258 def : PatFPSelectcc<SETULT, FCMP_CULT_S, FSEL_xS, FPR32>;
H A DLoongArchFloat64InstrInfo.td169 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
178 def : PatFPSetcc<SETULT, FCMP_CULT_D, FPR64>;
190 defm : PatFPBrcond<SETULT, FCMP_CULT_D, FPR64>;
204 def : PatStrictFsetccs<SETULT, FCMP_SULT_D, FPR64>;
223 def : PatFPSelectcc<SETULT, FCMP_CULT_D, FSEL_xD, FPR64>;
H A DLoongArchLASXInstrInfo.td1515 defm : PatCCXrUimm5<SETULT, "XVSLTI">;
1517 defm : PatCCXrXrU<SETULT, "XVSLT">;
1530 defm : PatCCXrXrF<SETULT, "XVFCMP_CULT">;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1520 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1546 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp250 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
262 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
279 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
303 case ISD::SETULT: in getICmpCondCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h85 case ISD::SETULT: in intCondCode2Icc()
129 case ISD::SETULT: in fpCondCode2Fcc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h178 case ISD::SETULT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td1022 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1029 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1033 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
1045 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
H A DRISCVInstrInfoVVLPatterns.td2186 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
2193 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
2197 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
2205 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
2209 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td298 def BLTU : Branch_RR<0x03, "bltu", SETULT>;
305 def BLTUI : Branch_RIU<0x0B, "bltui", SETULT>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3484 case ISD::SETULT: { in get32BitZExtCompare()
3657 case ISD::SETULT: { in get32BitSExtCompare()
3813 case ISD::SETULT: { in get64BitZExtCompare()
3976 case ISD::SETULT: { in get64BitSExtCompare()
4241 case ISD::SETULT: in SelectCC()
4268 case ISD::SETULT: in SelectCC()
4329 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
4361 case ISD::SETULT: return 0; in getCRIdxForSetCC()
4383 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4759 if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) { in mayUseP9Setb()
[all …]
H A DPPCInstrInfo.td3519 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3582 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3762 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3790 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3802 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3830 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
4025 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
4056 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
4077 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
4099 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
H A DPPCInstrSPE.td832 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
853 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp616 case ISD::SETULT: in NegateCC()
848 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td129 [{return (N->getZExtValue() == ISD::SETULT);}]>;
149 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp378 case ISD::SETULT: in softenSetCCOperands()
4040 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
4236 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
4242 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
4244 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
4658 case ISD::SETULT: in SimplifySetCC()
4681 case ISD::SETULT: in SimplifySetCC()
4897 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
5016 if ((Cond == ISD::SETULT && C1.isMinSignedValue()) || in SimplifySetCC()
10422 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
[all …]
H A DLegalizeIntegerTypes.cpp3003 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
3073 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
3184 Pred = ISD::SETULT; in ExpandIntRes_MINMAX()
3305 ISD::SETULT); in ExpandIntRes_ADDSUB()
3323 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
3396 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
4263 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
5191 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
5262 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
H A DSelectionDAGDumper.cpp479 case ISD::SETULT: return "setult"; in getOperationName()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp48 case ISD::SETULT: in ISDCCtoARCCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp952 case ISD::SETULT: in isLegalDSPCondCode()
1754 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1760 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1843 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
H A DMipsDSPInstrInfo.td1417 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1430 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp266 setCondCodeAction(ISD::SETULT, T, Expand); in initializeHVXLowering()
351 setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand); in initializeHVXLowering()
364 setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand); in initializeHVXLowering()
2410 SDValue Ovf = DAG.getSetCC(dl, PredTy, Add, A, ISD::SETULT); in emitHvxAddWithOverflow()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp89 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
92 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()

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