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Searched refs:SETULE (Results 1 – 25 of 55) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td189 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
199 def : PatFPSetcc<SETULE, FCMP_CULE_S, FPR32>;
219 defm : PatFPBrcond<SETULE, FCMP_CULE_S, FPR32>;
236 def : PatStrictFsetccs<SETULE, FCMP_SULE_S, FPR32>;
259 def : PatFPSelectcc<SETULE, FCMP_CULE_S, FSEL_xS, FPR32>;
H A DLoongArchFloat64InstrInfo.td169 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
179 def : PatFPSetcc<SETULE, FCMP_CULE_D, FPR64>;
191 defm : PatFPBrcond<SETULE, FCMP_CULE_D, FPR64>;
205 def : PatStrictFsetccs<SETULE, FCMP_SULE_D, FPR64>;
224 def : PatFPSelectcc<SETULE, FCMP_CULE_D, FSEL_xD, FPR64>;
H A DLoongArchLASXInstrInfo.td1509 defm : PatCCXrUimm5<SETULE, "XVSLEI">;
1511 defm : PatCCXrXrU<SETULE, "XVSLE">;
1526 defm : PatCCXrXrF<SETULE, "XVFCMP_CULE">;
H A DLoongArchLSXInstrInfo.td1609 defm : PatCCVrUimm5<SETULE, "VSLEI">;
1611 defm : PatCCVrVrU<SETULE, "VSLE">;
1626 defm : PatCCVrVrF<SETULE, "VFCMP_CULE">;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1521 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator
1546 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp251 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode()
263 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
275 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
295 case ISD::SETULE: in getICmpCondCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h87 case ISD::SETULE: in intCondCode2Icc()
133 case ISD::SETULE: in fpCondCode2Fcc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td81 defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
H A DWebAssemblyISelLowering.cpp121 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
256 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp617 case ISD::SETULE: in NegateCC()
850 SET_NEWCC(SETULE, JULE); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td131 [{return (N->getZExtValue() == ISD::SETULE);}]>;
151 [{return (N->getZExtValue() == ISD::SETULE);}]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3464 case ISD::SETULE: { in get32BitZExtCompare()
3637 case ISD::SETULE: { in get32BitSExtCompare()
3796 case ISD::SETULE: { in get64BitZExtCompare()
3959 case ISD::SETULE: { in get64BitSExtCompare()
4250 case ISD::SETULE: in SelectCC()
4277 case ISD::SETULE: in SelectCC()
4317 case ISD::SETULE: in getPredicateForSetCC()
4350 case ISD::SETULE: in getCRIdxForSetCC()
4382 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4390 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3540 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3847 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3864 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3876 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3893 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3906 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
3978 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)),
4005 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)),
4031 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
4060 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
[all …]
H A DPPCInstrSPE.td836 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
857 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp383 case ISD::SETULE: in softenSetCCOperands()
4042 } else if (Cond == ISD::CondCode::SETULE) { in optimizeSetCCOfSignedTruncationCheck()
4659 case ISD::SETULE: in SimplifySetCC()
4682 case ISD::SETULE: { in SimplifySetCC()
4877 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
5017 (Cond == ISD::SETULE && C1.isMaxSignedValue())) in SimplifySetCC()
5086 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
5087 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
5333 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
6756 DAG.getSetCC(DL, SETCCVT, D, CompTargetNode, ISD::SETULE); in prepareUREMEqFold()
[all …]
H A DSelectionDAGDumper.cpp480 case ISD::SETULE: return "setule"; in getOperationName()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td1024 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1031 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1039 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLEU", SETULE>;
H A DRISCVInstrInfoVVLPatterns.td2188 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2195 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2203 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2213 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp50 case ISD::SETULE: in ISDCCtoARCCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp953 case ISD::SETULE: in isLegalDSPCondCode()
1730 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1736 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1839 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td148 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
149 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
174 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
175 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
176 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
177 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
H A DMipsDSPInstrInfo.td1418 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1431 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp89 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
92 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
H A DAMDGPUInstructions.td378 def COND_ULE : PatFrag<(ops), (OtherVT SETULE)>;
H A DSIWholeQuadMode.cpp839 case ISD::SETULE: in lowerKillF32()

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