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Searched refs:SETUGT (Results 1 – 25 of 54) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1518 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
1546 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp248 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
264 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
281 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
307 case ISD::SETUGT: in getICmpCondCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h89 case ISD::SETUGT: in intCondCode2Icc()
131 case ISD::SETUGT: in fpCondCode2Fcc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3479 case ISD::SETUGT: in get32BitZExtCompare()
3652 case ISD::SETUGT: in get32BitSExtCompare()
3808 case ISD::SETUGT: in get64BitZExtCompare()
3971 case ISD::SETUGT: in get64BitSExtCompare()
4249 case ISD::SETUGT: in SelectCC()
4276 case ISD::SETUGT: in SelectCC()
4330 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
4362 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
4465 case ISD::SETUGT: in getVCmpInst()
4759 if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) { in mayUseP9Setb()
[all …]
H A DPPCInstrInfo.td3575 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3582 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3766 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3794 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3806 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3834 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
4046 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
4070 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
4091 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
4113 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
H A DPPCInstrSPE.td846 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
867 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td79 defm GT_U : ComparisonInt<SETUGT, "gt_u", 0x4b, 0x56>;
H A DWebAssemblyISelLowering.cpp121 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
256 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp388 case ISD::SETUGT: in softenSetCCOperands()
4046 } else if (Cond == ISD::CondCode::SETUGT) { in optimizeSetCCOfSignedTruncationCheck()
4236 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
4654 case ISD::SETUGT: in SimplifySetCC()
4679 case ISD::SETUGT: in SimplifySetCC()
4915 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
5008 if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) || in SimplifySetCC()
5086 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
10255 ISD::SETUGT); in expandFixedPointMul()
10422 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
[all …]
H A DSelectionDAGDumper.cpp477 case ISD::SETUGT: return "setugt"; in getOperationName()
H A DLegalizeIntegerTypes.cpp3069 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
3178 Pred = ISD::SETUGT; in ExpandIntRes_MINMAX()
3401 Cond = ISD::SETUGT; in ExpandIntRes_UADDSUBO()
4257 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT); in ExpandIntRes_MULFIX()
5193 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
5262 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat64InstrInfo.td168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchISelLowering.cpp165 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering()
265 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
279 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
311 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
325 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td1022 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1029 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1033 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
1041 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGTU", SETUGT>;
H A DRISCVInstrInfoVVLPatterns.td2186 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
2193 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
2197 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
2205 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
2209 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp258 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
263 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
359 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
395 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
954 case ISD::SETUGT: in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1421 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1434 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td121 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
141 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
H A DBPFISelLowering.cpp842 SET_NEWCC(SETUGT, JUGT); in EmitInstrWithCustomInserter()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp44 case ISD::SETUGT: in ISDCCtoARCCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1742 case ISD::SETUGT: in TranslateIntegerM68kCC()
1789 case ISD::SETUGT: in TranslateM68kCC()
1815 case ISD::SETUGT: // flipped in TranslateM68kCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td375 def COND_UGT : PatFrag<(ops), (OtherVT SETUGT)>;
H A DSIWholeQuadMode.cpp830 case ISD::SETUGT: in lowerKillF32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp823 case ISD::SETUGT: in IntCondCCodeToICC()

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