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Searched refs:SETUGE (Results 1 – 25 of 56) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1519 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1546 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp249 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
265 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
277 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
299 case ISD::SETUGE: in getICmpCondCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h91 case ISD::SETUGE: in intCondCode2Icc()
135 case ISD::SETUGE: in fpCondCode2Fcc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h180 case ISD::SETUGE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td1024 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1031 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1049 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
H A DRISCVInstrInfoVVLPatterns.td2188 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2195 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2203 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2213 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td297 def BGEU : Branch_RR<0x0B, "bgeu", SETUGE>;
304 def BGEUI : Branch_RIU<0x0F, "bgeui", SETUGE>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat64InstrInfo.td168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchISelLowering.cpp165 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering()
265 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
279 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
311 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
325 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3459 case ISD::SETUGE: in get32BitZExtCompare()
3632 case ISD::SETUGE: in get32BitSExtCompare()
3791 case ISD::SETUGE: in get64BitZExtCompare()
3954 case ISD::SETUGE: in get64BitSExtCompare()
4242 case ISD::SETUGE: in SelectCC()
4269 case ISD::SETUGE: in SelectCC()
4323 case ISD::SETUGE: in getPredicateForSetCC()
4348 case ISD::SETUGE: in getCRIdxForSetCC()
4382 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4426 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
H A DPPCInstrInfo.td3559 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3843 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3860 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3872 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3889 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3902 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3974 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)),
4001 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)),
4040 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
4066 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
[all …]
H A DPPCInstrSPE.td842 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
863 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1598 case ISD::SETUGE: in combineFMinMaxLegacyImpl()
2096 ISD::SETUGE); in LowerUDIVREM64()
2098 ISD::SETUGE); in LowerUDIVREM64()
2118 ISD::SETUGE); in LowerUDIVREM64()
2120 ISD::SETUGE); in LowerUDIVREM64()
2178 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
2184 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
2232 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2239 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
H A DAMDGPUInstructions.td376 def COND_UGE : PatFrag<(ops), (OtherVT SETUGE)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp257 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
262 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
358 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
394 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
955 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1420 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1433 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp644 case ISD::SETUGE: in intCCToAVRCC()
782 CC = ISD::SETUGE; in getAVRCmp()
790 CC = ISD::SETUGE; in getAVRCmp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td123 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
143 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
H A DBPFISelLowering.cpp844 SET_NEWCC(SETUGE, JUGE); in EmitInstrWithCustomInserter()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp478 case ISD::SETUGE: return "setuge"; in getOperationName()
H A DTargetLowering.cpp393 case ISD::SETUGE: in softenSetCCOperands()
4050 } else if (Cond == ISD::CondCode::SETUGE) { in optimizeSetCCOfSignedTruncationCheck()
4655 case ISD::SETUGE: in SimplifySetCC()
4680 case ISD::SETUGE: in SimplifySetCC()
4857 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
5009 (Cond == ISD::SETUGE && C1.isMinSignedValue())) in SimplifySetCC()
5085 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
5098 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
5340 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
9989 return buildMinMax(ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE); in expandIntMINMAX()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp46 case ISD::SETUGE: in ISDCCtoARCCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1740 case ISD::SETUGE: in TranslateIntegerM68kCC()
1790 case ISD::SETUGE: in TranslateM68kCC()
1819 case ISD::SETUGE: // flipped in TranslateM68kCC()

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