| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF2.td | 379 defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, BF32, MVC32>; 396 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16), 398 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), 400 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), FPR32Op:$rx, FPR32Op:$false),
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| H A D | CSKYInstrInfoF1.td | 359 defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, BF32, MVC32>; 376 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16), 378 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1511 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 241 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode() 265 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.h | 119 case ISD::SETOGE: in fpCondCode2Fcc()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrFloat.td | 90 defm GE : ComparisonFP<SETOGE, "ge ", 0x60, 0x66>;
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| H A D | WebAssemblyInstrSIMD.td | 739 defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
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| H A D | LoongArchFloat64InstrInfo.td | 168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
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| H A D | LoongArchISelLowering.cpp | 165 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering() 278 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering() 324 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 469 case ISD::SETOGE: return "setoge"; in getOperationName()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4240 case ISD::SETOGE: in SelectCC() 4267 case ISD::SETOGE: in SelectCC() 4305 case ISD::SETOGE: in getPredicateForSetCC() 4356 case ISD::SETOGE: in getCRIdxForSetCC() 4380 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; in getVCmpInst() 4391 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst() 4411 case ISD::SETOGE: in getVCmpInst()
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| H A D | PPCISelLowering.cpp | 670 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering() 671 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering() 1220 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand); in PPCTargetLowering() 8108 case ISD::SETOGE: in LowerSELECT_CC() 8146 case ISD::SETOGE: in LowerSELECT_CC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructions.td | 363 def COND_OGE : PatFrags<(ops), [(OtherVT SETOGE), (OtherVT SETGE)]>;
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| H A D | SIWholeQuadMode.cpp | 859 case ISD::SETOGE: in lowerKillF32()
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| H A D | AMDGPUISelLowering.cpp | 1606 case ISD::SETOGE: in combineFMinMaxLegacyImpl() 1952 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24() 2477 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 255 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in MipsSETargetLowering() 260 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering() 392 setCondCodeAction(ISD::SETOGE, Ty, Expand); in addMSAFloatType()
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| H A D | MipsMSAInstrInfo.td | 128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 129 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 855 case ISD::SETOGE: in IntCondCCodeToICC()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 793 def SETOGE : CondCode<"FCMP_OGE">; 1426 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 346 setCondCodeAction(ISD::SETOGE, MVT::v64f16, Expand); in initializeHVXLowering() 359 setCondCodeAction(ISD::SETOGE, MVT::v32f32, Expand); in initializeHVXLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 563 case ISD::SETOGE: in getPTXCmpMode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1999 defm FCMGE_PPzZZ : sve_fp_3op_p_pd_cc<0b000, "fcmge", SETOGE, SETGE, SETOLE, SETLE>; 2007 defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge", SETOGE, SETGE, SETOLE, SETLE>; 2010 defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle", SETOLE, SETLE, SETOGE, SETGE>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1812 case ISD::SETOGE: in TranslateM68kCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1572 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
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