Home
last modified time | relevance | path

Searched refs:SETLT (Results 1 – 25 of 65) sorted by relevance

123

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td189 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
202 def : PatFPSetcc<SETLT, FCMP_CLT_S, FPR32>;
222 defm : PatFPBrcond<SETLT, FCMP_CLT_S, FPR32>;
239 def : PatStrictFsetccs<SETLT, FCMP_SLT_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td169 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
182 def : PatFPSetcc<SETLT, FCMP_CLT_D, FPR64>;
194 defm : PatFPBrcond<SETLT, FCMP_CLT_D, FPR64>;
208 def : PatStrictFsetccs<SETLT, FCMP_SLT_D, FPR64>;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1529 SETLT, // 1 X 1 0 0 True if less than enumerator
1540 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfa.td207 def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S, f32>;
230 def: PatSetCC<FPR64, strict_fsetcc, SETLT, FLTQ_D, f64>;
258 def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H, f16>;
H A DRISCVInstrInfoD.td397 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
404 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_D, Ext>;
424 def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D, f64>;
444 def : PatSetCC<FPR64INX, any_fsetccs, SETLT, FLT_D_INX, f64>;
464 def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64>;
H A DRISCVISelDAGToDAG.h174 case ISD::SETLT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoZfh.td353 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
360 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_H, Ext>;
397 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_H, Ext>;
H A DRISCVInstrInfoVSDPatterns.td1021 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1028 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
1032 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
1043 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLE", SETLT,
1372 defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
H A DRISCVInstrInfoF.td604 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
611 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_S, Ext>;
648 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_S, Ext>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h77 case ISD::SETLT: in intCondCode2Icc()
109 case ISD::SETLT: in fpCondCode2Fcc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp262 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
278 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
301 case ISD::SETLT: in getICmpCondCode()
H A DTargetLoweringBase.cpp714 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
715 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
716 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
717 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in InitCmpLibcallCCs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td296 def BLT : Branch_RR<0x02, "blt", SETLT>;
303 def BLTI : Branch_RI<0x0A, "blti", SETLT>;
310 def BLTZ : Branch_RZ<0x01, 0x02, "bltz", SETLT>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td389 defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, BF32, MVC32>;
438 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
440 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)),
442 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td369 defm : BRCond_Bin<SETLT, "FCMPLT", BT32, BF32, MVC32>;
412 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
414 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp618 case ISD::SETLT: in NegateCC()
847 SET_NEWCC(SETLT, JSLT); in EmitInstrWithCustomInserter()
858 CC == ISD::SETLT || in EmitInstrWithCustomInserter()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp263 setCondCodeAction(ISD::SETLT, T, Expand); in initializeHVXLowering()
343 setCondCodeAction(ISD::SETLT, MVT::v64f16, Expand); in initializeHVXLowering()
356 setCondCodeAction(ISD::SETLT, MVT::v32f32, Expand); in initializeHVXLowering()
2590 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2591 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2600 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV60()
2642 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2643 SDValue Q1 = DAG.getSetCC(dl, PredTy, B, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2656 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62()
2788 SDValue Neg = DAG.getSetCC(dl, PredTy, Inp, Zero, ISD::SETLT); in ExpandHvxFpToInt()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp336 case ISD::SETLT: in softenSetCCOperands()
813 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyMultipleUseDemandedBits()
4666 case ISD::SETLT: in SimplifySetCC()
4897 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
5012 ISD::SETLT); in SimplifySetCC()
6129 SDValue Cmp = DAG.getSetCC(DL, CCVT, N0, Zero, ISD::SETLT); in buildSDIVPow2WithCMov()
7088 return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); in getSqrtInputTest()
8147 Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT, in expandFP_TO_UINT()
8151 Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT); in expandFP_TO_UINT()
10274 ISD::SETLT); in expandFixedPointMul()
[all …]
H A DLegalizeIntegerTypes.cpp3071 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3112 DAG.getSetCC(DL, CCT, LHSH, DAG.getConstant(0, DL, NVT), ISD::SETLT); in ExpandIntRes_MINMAX()
3172 Pred = ISD::SETLT; in ExpandIntRes_MINMAX()
3642 DAG.getConstant(0, dl, NVT), ISD::SETLT); in ExpandIntRes_ABS()
4120 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT); in ExpandIntRes_MULFIX()
4261 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
4274 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
4288 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT); in ExpandIntRes_MULFIX()
5179 if ((CCCode == ISD::SETLT && CST->isZero()) || // X < 0 in IntegerExpandSetCCOperands()
5190 case ISD::SETLT: in IntegerExpandSetCCOperands()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3430 case ISD::SETLT: { in get32BitZExtCompare()
3609 case ISD::SETLT: { in get32BitSExtCompare()
3764 case ISD::SETLT: { in get64BitZExtCompare()
3924 case ISD::SETLT: { in get64BitSExtCompare()
4237 case ISD::SETLT: in SelectCC()
4264 case ISD::SETLT: in SelectCC()
4315 case ISD::SETLT: in getPredicateForSetCC()
4521 case ISD::SETLT: { in trySETCC()
4560 case ISD::SETLT: { in trySETCC()
4792 case ISD::SETLT: in mayUseP9Setb()
[all …]
H A DPPCInstrInfo.td3517 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3657 defm : ExtSetCCPat<SETLT,
3689 defm : ExtSetCCPat<SETLT,
3764 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3792 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3804 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3832 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3919 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
3963 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),
3990 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td76 defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1732 case ISD::SETLT: in TranslateIntegerM68kCC()
1762 if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) { in TranslateM68kCC()
1766 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1817 case ISD::SETLT: in TranslateM68kCC()
3462 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3517 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1252 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1269 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1277 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1324 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, in MSP430TargetLowering()
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, in MSP430TargetLowering()
1109 case ISD::SETLT: in EmitCMP()

123