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Searched refs:SCLK (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/sys/contrib/device-tree/Bindings/iio/resolver/
H A Dad2s90.txt19 application of SCLK, as also specified. And since the delay is not
20 implemented in the spi code, to satisfy it, SCLK's period should be at most
H A Dadi,ad2s90.yaml27 application of SCLK, as also specified. And since the delay is not
28 implemented in the spi code, to satisfy it, SCLK's period should be at
/freebsd-14.2/sys/contrib/device-tree/Bindings/sound/
H A Dpcm512x.txt19 - clocks : A clock specifier for the clock connected as SCLK. If this
27 external connection from the pll-out pin to the SCLK pin is assumed.
H A Dcs35l34.txt45 SCLK. Otherwise, data is on the falling edge of SCLK.
H A Dsgtl5000.txt40 - sclk-strength: the SCLK pad strength. Possible values are:
H A Dsgtl5000.yaml71 The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
/freebsd-14.2/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dmicrochip,pic32-clock.h18 #define SCLK 7 macro
/freebsd-14.2/sys/contrib/device-tree/Bindings/spi/
H A Dspi_oc_tiny.txt9 the input clock to SCLK.
H A Dspi-rockchip.yaml71 Nano seconds to delay after the SCLK edge before sampling Rx data
/freebsd-14.2/sys/contrib/device-tree/Bindings/i2c/
H A Drenesas,iic-emev2.txt7 - clocks : phandle to the IP core SCLK
/freebsd-14.2/sys/dev/sym/
H A Dsym_defs.h447 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
H A Dsym_hipd.c7011 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Darmada-385-turris-omnia.dts556 /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */