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Searched refs:SCALAR_TO_VECTOR (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp100 case ISD::SCALAR_TO_VECTOR: in Select()
H A DSIISelLowering.cpp333 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
365 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
379 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
393 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
407 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
421 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
632 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
908 ISD::SCALAR_TO_VECTOR, in SITargetLowering()
5567 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
6926 if (VecBC.getOpcode() == ISD::SCALAR_TO_VECTOR) { in lowerEXTRACT_VECTOR_ELT()
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H A DAMDGPUISelDAGToDAG.cpp232 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo); in matchLoadD16FromBuildVector()
472 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); in SelectBuildVector()
543 case ISD::SCALAR_TO_VECTOR: in Select()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h620 SCALAR_TO_VECTOR, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp63 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
252 SDValue OtherVal = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, OtherVT, in ScalarizeVecRes_FFREXP()
329 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo)); in ScalarizeVecRes_OverflowOp()
779 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
796 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_UnaryOp_StrictFP()
862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res); in ScalarizeVecOp_VSETCC()
908 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_STRICT_FP_ROUND()
1009 case ISD::SCALAR_TO_VECTOR: in SplitVectorResult()
1875 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { in SplitVecRes_ScalarOp()
4086 case ISD::SCALAR_TO_VECTOR: in WidenVectorResult()
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H A DLegalizeDAG.cpp415 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
1850 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V); in ExpandBVWithShuffles()
1958 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
2013 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
2016 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
3397 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
5527 case ISD::SCALAR_TO_VECTOR: { in PromoteNode()
H A DSelectionDAGDumper.cpp308 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; in getOperationName()
H A DDAGCombiner.cpp2045 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); in visit()
5869 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && in hoistLogicOpWithSameOpcodeHands()
22206 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22299 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
22443 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
23849 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitCONCAT_VECTORS()
24770 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineShuffleOfScalars()
25440 SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO); in visitVECTOR_SHUFFLE()
25449 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) in visitVECTOR_SHUFFLE()
25461 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR || in visitVECTOR_SHUFFLE()
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H A DLegalizeIntegerTypes.cpp135 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
1790 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
5103 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
H A DSelectionDAG.cpp3234 case ISD::SCALAR_TO_VECTOR: { in computeKnownBits()
5823 case ISD::SCALAR_TO_VECTOR: in getNode()
H A DTargetLowering.cpp1143 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedBits()
3067 case ISD::SCALAR_TO_VECTOR: { in SimplifyDemandedVectorElts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp257 case ISD::SCALAR_TO_VECTOR: in getIdiomaticVectorType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2433 ISD::SCALAR_TO_VECTOR, in X86TargetLowering()
5568 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR && in getTargetShuffleAndZeroables()
5859 case ISD::SCALAR_TO_VECTOR: in getFauxShuffleMask()
5866 if (Opcode != ISD::SCALAR_TO_VECTOR) { in getFauxShuffleMask()
5918 if (Opcode == ISD::SCALAR_TO_VECTOR) { in getFauxShuffleMask()
6341 if (Opcode == ISD::SCALAR_TO_VECTOR) in getShuffleScalarElt()
6716 case ISD::SCALAR_TO_VECTOR: in findEltLoadSrc()
38099 V2.getOpcode() == ISD::SCALAR_TO_VECTOR && in combineX86ShuffleChain()
54795 ISD::SCALAR_TO_VECTOR || in combineConcatVectorOps()
54797 ISD::SCALAR_TO_VECTOR; in combineConcatVectorOps()
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H A DX86ISelLoweringCall.cpp820 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, in LowerReturn()
1063 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, ValReturned); in lowerRegToMasks()
1404 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val) in LowerMemArgument()
2170 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); in LowerCall()
H A DX86ISelDAGToDAG.cpp1261 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1263 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
H A DX86FastISel.cpp2637 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp869 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
976 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
977 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
991 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
3033 UI->getOpcode() != ISD::SCALAR_TO_VECTOR && in usePartialVectorLoads()
9229 if (InputLoad->getOpcode() == ISD::SCALAR_TO_VECTOR || in getNormalLoadInput()
15224 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR) in isScalarToVec()
15229 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR) in isScalarToVec()
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H A DPPCISelDAGToDAG.cpp5971 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR && in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp434 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
546 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in SystemZTargetLowering()
547 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in SystemZTargetLowering()
5584 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
5847 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
5871 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerVECTOR_SHUFFLE()
6043 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerShift()
6193 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1027 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR); in AArch64TargetLowering()
5122 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, N); in LowerINTRINSIC_WO_CHAIN()
12218 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) in LowerVECTOR_SHUFFLE()
13090 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
13384 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0); in LowerBUILD_VECTOR()
19276 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, Op1); in performAddSubIntoVectorOp()
19279 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i64, Op0); in performAddSubIntoVectorOp()
19669 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op); in tryCombineShiftImm()
22890 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); in performSelectCombine()
24172 case ISD::SCALAR_TO_VECTOR: in PerformDAGCombine()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp726 ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
846 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
987 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1040 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1106 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in RISCVTargetLowering()
1257 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
6002 case ISD::SCALAR_TO_VECTOR: { in LowerOperation()
6008 SDValue V = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, WideVT, Scalar); in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp337 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal); in addMVEVectorTypes()
403 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in addMVEVectorTypes()
449 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in addMVEVectorTypes()
6042 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
6044 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
8024 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
8823 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { in LowerVECTOR_SHUFFLE()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td740 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1642 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()