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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1231 bits<5> Rn;
5169 def : Pat<(vnot (AArch64cmeqz VT:$Rn)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
6137 (FADDPv8f16 (FADDPv8f16 V128:$Rn, V128:$Rn), V128:$Rn),
6145 (FADDPv4f32 V128:$Rn, V128:$Rn),
6859 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
6864 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
6868 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
6872 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
6876 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
6880 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
[all …]
H A DAArch64InstrAtomics.td74 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
77 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
90 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
93 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
106 (LDRWui GPR64sp:$Rn, uimm12s4:$offset)>;
109 (LDURWi GPR64sp:$Rn, simm9:$offset)>;
122 (LDRXui GPR64sp:$Rn, uimm12s8:$offset)>;
125 (LDURXi GPR64sp:$Rn, simm9:$offset)>;
136 (LDRSui GPR64sp:$Rn, uimm12s8:$offset)>;
139 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
[all …]
H A DAArch64InstrGISel.td466 (ADDPv2i32 V64:$Rn, V64:$Rn), dsub),
479 (ADDPv2i32 V64:$Rn, V64:$Rn), dsub),
491 (SMAXPv2i32 V64:$Rn, V64:$Rn), dsub),
498 (SMINPv2i32 V64:$Rn, V64:$Rn), dsub),
505 (UMAXPv2i32 V64:$Rn, V64:$Rn), dsub),
512 (UMINPv2i32 V64:$Rn, V64:$Rn), dsub),
561 (LD1Rv8b GPR64sp:$Rn)>;
565 (LD1Rv4h GPR64sp:$Rn)>;
567 (LD1Rv8h GPR64sp:$Rn)>;
569 (LD1Rv2s GPR64sp:$Rn)>;
[all …]
H A DAArch64InstrFormats.td1999 bits<5> Rn;
2013 bits<5> Rn;
2033 bits<5> Rn;
2043 bits<5> Rn;
2062 bits<5> Rn;
2292 bits<5> Rn;
2324 bits<5> Rn;
2352 bits<5> Rn;
2410 : I<(outs), (ins GPR64:$Rn), asm, "\t$Rn", "", []>,
2412 bits<5> Rn;
[all …]
H A DSVEInstrFormats.td1295 bits<5> Rn;
2853 bits<5> Rn;
5341 bits<5> Rn;
5362 bits<5> Rn;
5410 bits<5> Rn;
5762 bits<5> Rn;
5800 bits<5> Rn;
6150 bits<5> Rn;
6187 bits<5> Rn;
6220 bits<5> Rn;
[all …]
H A DSMEInstrFormats.td467 bits<5> Rn;
644 bits<5> Rn;
773 bits<5> Rn;
3144 !if(opc{7}, (ins ZTR:$ZTt, GPR64sp:$Rn), (ins GPR64sp:$Rn)),
3147 bits<5> Rn;
4481 bits<5> Rn;
4506 bits<5> Rn;
4532 bits<5> Rn;
4589 bits<5> Rn;
4614 bits<5> Rn;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td459 bits<4> Rn;
471 bits<4> Rn;
510 bits<4> Rn;
543 bits<4> Rn;
555 bits<4> Rn;
569 bits<4> Rn;
609 bits<4> Rn;
621 bits<4> Rn;
633 bits<4> Rn;
2568 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
[all …]
H A DARMInstrInfo.td1866 bits<4> Rn;
1879 bits<4> Rn;
2227 bits<4> Rn;
2763 bits<4> Rn;
3825 bits<4> Rn;
3842 bits<4> Rn;
3939 bits<4> Rn;
4059 bits<4> Rn;
4074 bits<4> Rn;
4092 bits<4> Rn;
[all …]
H A DARMInstrThumb.td828 bits<3> Rn;
856 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
858 bits<3> Rn;
901 bits<3> Rn;
921 bits<3> Rn;
930 bits<3> Rn;
1057 def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
1128 bits<3> Rn;
1146 bits<4> Rn;
1249 bits<3> Rn;
[all …]
H A DARMInstrNEON.td604 let Inst{4} = Rn{4};
677 let Inst{4} = Rn{4};
887 let Inst{4} = Rn{4};
906 let Inst{4} = Rn{4};
1134 let Inst{5} = Rn{4};
1135 let Inst{4} = Rn{4};
1296 let Inst{4} = Rn{4};
1308 let Inst{5} = Rn{5};
1321 let Inst{5} = Rn{5};
1349 let Inst{5} = Rn{5};
[all …]
H A DARMInstrCDE.td84 dag Rn;
136 bits<4> Rn;
140 let Inst{19-16} = Rn{3-0};
154 bits<4> Rn;
159 let Inst{19-16} = Rn{3-0};
170 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
178 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
189 let Iops2 = !con(IOpsPrefix, ops.Rn);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
475 let Rn = (ins regclass:$Vn);
[all …]
H A DARMInstrFormats.td805 bits<4> Rn;
823 bits<4> Rn;
935 bits<4> Rn;
966 bits<4> Rn;
988 bits<4> Rn;
1060 bits<4> Rn;
1094 bits<4> Rn;
1519 bits<4> Rn;
1697 bits<4> Rn;
1738 bits<4> Rn;
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
20 // | | uopc Rd, Rn, T0 - P01 - 1
23 // and one cycle after the result in Rn is available. The micro-ops can execute
26 // that the resource P01 is needed and that the latency to Rn is different than
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrVFP.td242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
287 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
317 NoItinerary, "vlldm${p}\t$Rn", "", []>,
330 NoItinerary, "vlstm${p}\t$Rn", "", []>,
375 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
382 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2872 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> {
2873 bits<4> Rn;
[all …]
H A DARMInstrMVE.td5761 iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src", size,
5765 bits<4> Rn;
5800 bits<4> Rn;
5832 bits<4> Rn;
5979 bits<4> Rn;
6262 asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
6263 bits<4> Rn;
6290 asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
6291 bits<4> Rn;
6907 bits<4> Rn;
[all …]
H A DThumb2SizeReduction.cpp466 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
471 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
479 .addReg(Rn, RegState::Define) in ReduceLoadStore()
480 .addReg(Rn) in ReduceLoadStore()
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp2498 if (wback && ((Rn == 15) || (Rn == Rt))) in EmulateSTRRtSP()
3101 uint64_t Rn = in EmulateADDImmThumb() local
3306 if (Rn == 15) in EmulateCMNImm()
3423 if (Rn == 15) in EmulateCMPImm()
3847 Rn = Rd; in EmulateShiftReg()
4228 addr_t Rn = in EmulateLDMDB() local
4338 addr_t Rn = in EmulateLDMIB() local
4450 Rn = 13; in EmulateLDRRtRnImm()
4915 addr_t Rn = in EmulateSTMDB() local
9750 uint32_t Rn; in EmulateTEQImm() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2104 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2240 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2254 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2273 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2288 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2306 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
5125 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) in DecodeDoubleRegStore()
5150 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; in DecodeLDRPreImm()
5889 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2LDRDPreInstruction()
5926 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2STRDPreInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp955 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
1054 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
1149 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
1208 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
1396 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
1406 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeExclusiveLdStInstruction() local
1489 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodePairLdStInstruction() local
1613 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) in DecodePairLdStInstruction()
1645 if (writeback && Rt == Rn && Rn != 31) { in DecodeAuthLoadInstruction()
2055 if (Rd == Rs || Rs == Rn || Rd == Rn) in DecodeCPYMemOpInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td223 def : Pat<(i32 (fp_to_sint (round sFPR32Op:$Rn))),
224 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
226 def : Pat<(i32 (fp_to_uint (round sFPR32Op:$Rn))),
227 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
229 def : Pat<(i32 (fp_to_sint (round sFPR64Op:$Rn))),
230 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
232 def : Pat<(i32 (fp_to_uint (round sFPR64Op:$Rn))),
242 def : Pat<(i32 (fp_to_sint sFPR32Op:$Rn)),
245 def : Pat<(i32 (fp_to_uint sFPR32Op:$Rn)),
248 def : Pat<(i32 (fp_to_sint sFPR64Op:$Rn)),
[all …]
/freebsd-14.2/sys/arm64/arm64/
H A Dundefined.c207 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
224 Rn = (insn & 0xf0000) >> 16; in swp_emulate()
229 vaddr = regs[Rn] & 0xffffffff; in swp_emulate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kSchedule.td17 let LoadLatency = 4; // Word (Rn)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp922 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
924 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1058 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue() local
1063 return (Rn << 3) | Qm; in getMveAddrModeRQOpValue()
1276 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local
1295 Binary |= Rn << 13; in getLdStSORegOpValue()
1381 return (Rn << 9) | (1 << 13); in getAddrMode3OpValue()
1383 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local
1391 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); in getAddrMode3OpValue()
1420 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeISOpValue() local
[all …]
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp619 const uint32_t Rn = Bits32(opcode, 9, 5); in EmulateADDSUBImm() local
625 const uint32_t n = UInt(Rn); in EmulateADDSUBImm()
700 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP() local
703 integer n = UInt(Rn); in EmulateLDPSTP()
/freebsd-14.2/secure/caroot/trusted/
H A DTelekom_Security_TLS_ECC_Root_2020.pem66 z6fLHgIwN0GMZt9Ba9aDAEH9L1r3ULRn0SyocddDypwnJJGDSA3PzfdUga/sf+Rn

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