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Searched refs:Rm (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td454 // ADD <Rm>, sp
466 // ADD sp, <Rm>
471 bits<4> Rm;
900 bits<3> Rm;
909 bits<3> Rm;
929 bits<3> Rm;
941 bits<3> Rm;
952 bits<3> Rm;
1145 bits<4> Rm;
1224 bits<4> Rm;
[all …]
H A DARMInstrThumb2.td524 bits<4> Rm;
534 bits<4> Rm;
544 bits<4> Rm;
583 bits<4> Rm;
596 bits<4> Rm;
610 bits<4> Rm;
622 bits<4> Rm;
634 bits<4> Rm;
676 bits<4> Rm;
2568 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
[all …]
H A DARMInstrInfo.td1839 bits<4> Rm;
1865 bits<4> Rm;
2228 bits<4> Rm;
3605 bits<4> Rm;
3619 bits<4> Rm;
3941 bits<4> Rm;
4060 bits<4> Rm;
4075 bits<4> Rm;
4232 bits<4> Rm;
4296 bits<4> Rm;
[all …]
H A DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
676 let Rm = 0b1111;
739 let Rm = 0b1111;
803 let Rm = 0b1111;
886 let Rm = 0b1111;
946 let Rm = 0b1111;
1038 let Rm = 0b1111;
1050 let Rm = 0b1111;
1148 let Rm = 0b1111;
[all …]
H A DARMInstrCDE.td85 dag Rm;
155 bits<4> Rm;
160 let Inst{15-12} = Rm{3-0};
171 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
179 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
476 let Rm = (ins regclass:$Vm);
484 let Rm = (ins regclass:$Qm);
498 let Iops2 = !con(IOpsPrefix, ops.Rm);
499 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
22 // Rd after a minimum of three cycles after the result in Rm and Rs is available
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrFormats.td803 // {11-0} imm12/Rm
821 // {11-0} imm12/Rm
842 // {11-0} imm12/Rm
896 // {3-0} imm3_0/Rm
967 bits<4> Rm;
989 bits<4> Rm;
1029 bits<4> Rm;
1045 bits<4> Rm;
1061 bits<4> Rm;
1095 bits<4> Rm;
[all …]
H A DARMInstrMVE.td485 bits<4> Rm;
487 let Inst{15-12} = Rm{3-0};
534 bits<4> Rm;
537 let Inst{15-12} = Rm{3-0};
4277 bits<4> Rm;
4290 let Inst{3-0} = Rm{3-0};
5184 bits<4> Rm;
5211 bits<4> Rm;
5799 bits<4> Rm;
6652 bits<4> Rm;
[all …]
H A DARMBaseInstrInfo.cpp3509 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3516 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3546 if (!Rm) in getNumMicroOpsSwiftLdSt()
3548 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3558 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3577 if (Rm == 0) in getNumMicroOpsSwiftLdSt()
3580 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3597 if (Rm) in getNumMicroOpsSwiftLdSt()
3605 if (Rm) in getNumMicroOpsSwiftLdSt()
3623 if (Rm) in getNumMicroOpsSwiftLdSt()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td68 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
71 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
84 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
87 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
100 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
103 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
116 (LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
119 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
130 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
133 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
[all …]
H A DAArch64InstrFormats.td2034 bits<5> Rm;
2353 bits<5> Rm;
2436 bits<5> Rm;
2442 let Inst{4-0} = Rm; // op4 (Rm)
2481 bits<5> Rm;
2536 bits<5> Rm;
2606 bits<5> Rm;
2646 bits<5> Rm;
2677 bits<5> Rm;
2829 bits<5> Rm;
[all …]
H A DAArch64InstrInfo.td2097 def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>;
2098 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>;
2099 def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>;
2100 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>;
2404 def : Pat<(int_aarch64_irg_sp i64:$Rm), (IRGstack SP, i64:$Rm)>;
2521 def : Pat<(int_aarch64_cls64 GPR64:$Rm), (EXTRACT_SUBREG (CLSXr GPR64:$Rm), sub_32)>;
5489 def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>;
5492 def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>;
5493 def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>;
9365 bits<5> Rm;
[all …]
H A DSVEInstrFormats.td1667 bits<5> Rm;
5340 bits<5> Rm;
5361 bits<5> Rm;
5409 bits<5> Rm;
5693 bits<5> Rm;
5799 bits<5> Rm;
6252 bits<5> Rm;
6278 bits<5> Rm;
6300 bits<5> Rm;
6365 bits<5> Rm;
[all …]
H A DAArch64InstrGISel.td537 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
539 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
542 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
544 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
H A DSMEInstrFormats.td464 bits<5> Rm;
472 let Inst{20-16} = Rm;
488 gpr_ty:$Rm),
641 bits<5> Rm;
649 let Inst{20-16} = Rm;
4479 bits<5> Rm;
4484 let Inst{20-16} = Rm;
4504 bits<5> Rm;
4509 let Inst{20-16} = Rm;
4587 bits<5> Rm;
[all …]
H A DAArch64SchedPredicates.td298 // MOV Rd, Rm =>
299 // ORR Rd, ZR, Rm, LSL #0
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2269 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
3215 if (Rm != 0xD && Rm != 0xF && in DecodeVLDInstruction()
3589 if (Rm != 0xF) { in DecodeVLD1DupInstruction()
3601 if (Rm != 0xD && Rm != 0xF && in DecodeVLD1DupInstruction()
3642 if (Rm != 0xF) in DecodeVLD2DupInstruction()
3649 if (Rm != 0xD && Rm != 0xF) { in DecodeVLD2DupInstruction()
3674 if (Rm != 0xF) { in DecodeVLD3DupInstruction()
3683 if (Rm == 0xD) in DecodeVLD3DupInstruction()
3727 if (Rm != 0xF) { in DecodeVLD4DupInstruction()
3736 if (Rm == 0xD) in DecodeVLD4DupInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp2135 if (Rm == 15) in EmulateBLXRm()
2144 if (Rm == 15) in EmulateBLXRm()
6574 uint32_t Rm = in EmulateLDRRegister() local
7001 uint32_t Rm = in EmulateLDRBRegister() local
7413 uint64_t Rm = in EmulateLDRHRegister() local
7817 uint64_t Rm = in EmulateLDRSBRegister() local
8245 uint64_t Rm = in EmulateLDRSHRegister() local
8375 uint64_t Rm = in EmulateSXTB() local
8460 uint64_t Rm = in EmulateSXTH() local
8545 uint64_t Rm = in EmulateUXTB() local
[all …]
/freebsd-14.2/sys/arm64/arm64/
H A Dundefined.c207 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
226 Rm = (insn & 0xf); in swp_emulate()
230 val = regs[Rm]; in swp_emulate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1055 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
1083 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1104 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1657 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1671 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1677 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1683 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1689 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
2075 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeSETMemOpInstruction() local
2080 if (Rd == Rm || Rm == Rn || Rd == Rn) in DecodeSETMemOpInstruction()
[all …]
/freebsd-14.2/crypto/openssl/test/certs/
H A Dbadalt8-key.pem5 PQPxnY2uLSRcMZ7n6FuAs+Rm+eHS+8kKTsARDaKo7g2l7i4egPHcZc2jYlvoEo1/
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp863 unsigned Rm = MI->getOperand(2).getReg(); in printRangePrefetchAlias() local
866 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) in printRangePrefetchAlias()
867 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, in printRangePrefetchAlias()
887 O << getRegisterName(Rm); in printRangePrefetchAlias()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp923 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue() local
924 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1277 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue() local
1294 uint32_t Binary = Rm; in getLdStSORegOpValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp953 int Rn = 0, Rm = 0; in buildHvxVectorReg() local
967 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
971 Rm = 0; in buildHvxVectorReg()
974 Rm += 4; in buildHvxVectorReg()
978 Sm = DAG.getConstant(Rm, dl, MVT::i32); in buildHvxVectorReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td1303 (instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"),

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