Searched refs:ResRegs (Results 1 – 4 of 4) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 548 ArrayRef<Register> ResRegs = GetOrCreateVRegs(Call); in lowerInlineAsm() local
549 if (ResRegs.size() != OutputOperands.size()) { in lowerInlineAsm()
554 for (unsigned int i = 0, e = ResRegs.size(); i < e; i++) { in lowerInlineAsm()
571 LLT ResTy = MRI->getType(ResRegs[i]); in lowerInlineAsm()
579 MIRBuilder.buildTrunc(ResRegs[i], Tmp1Reg); in lowerInlineAsm()
581 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
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| H A D | CallLowering.cpp | 91 ArrayRef<Register> ResRegs, in lowerCall() argument
160 Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, getAttributesForReturn(CB)}; in lowerCall()
167 ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]); in lowerCall()
191 MIRBuilder.buildAssertAlign(ResRegs[0], ReturnHintAlignReg, in lowerCall()
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| H A D | IRTranslator.cpp | 1517 ArrayRef<Register> ResRegs = getOrCreateVRegs(U); in translateSelect() local
1525 for (unsigned i = 0; i < ResRegs.size(); ++i) { in translateSelect()
1526 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
1800 ArrayRef<Register> ResRegs = getOrCreateVRegs(CI); in translateOverflowIntrinsic() local
1802 Op, {ResRegs[0], ResRegs[1]}, in translateOverflowIntrinsic()
2851 ArrayRef<Register> ResRegs = getOrCreateVRegs(LP); in translateLandingPad() local
2852 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
2861 MIRBuilder.buildCast(ResRegs[1], PtrVReg); in translateLandingPad()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 585 ArrayRef<Register> ResRegs,
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