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Searched refs:ResNo (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h695 ValueTypeByHwMode getType(unsigned ResNo) const { in getType() argument
696 return Types[ResNo].getValueTypeByHwMode(); in getType()
700 return Types[ResNo]; in getExtType()
702 TypeSetByHwMode &getExtType(unsigned ResNo) { return Types[ResNo]; } in getExtType() argument
703 void setType(unsigned ResNo, const TypeSetByHwMode &T) { Types[ResNo] = T; } in setType() argument
705 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
708 bool hasConcreteType(unsigned ResNo) const { in hasConcreteType() argument
709 return Types[ResNo].isValueTypeByHwMode(false); in hasConcreteType()
712 return Types[ResNo].empty(); in isTypeCompletelyUnknown()
716 unsigned getResultIndex(unsigned ResNo) const { return ResultPerm[ResNo]; } in getResultIndex() argument
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H A DCodeGenDAGPatterns.cpp1595 unsigned &ResNo) { in getOperandNum() argument
1598 ResNo = OpNo; in getOperandNum()
1632 return NodeToApply->UpdateNodeType(ResNo, VVT, TP); in ApplyTypeConstraint()
1649 return (int)NodeToApply->UpdateNodeType(ResNo, in ApplyTypeConstraint()
1749 return UpdateNodeType(ResNo, MVT::iPTR, TP); in UpdateNodeTypeFromInst()
2278 assert(ResNo == 0 && "This node only has one result!"); in getImplicitType()
2297 assert(ResNo == 0 && "This node only has one result!"); in getImplicitType()
2573 for (unsigned ResNo = 0; ResNo != NumResultsToAdd; ++ResNo) in ApplyTypeConstraints() local
2574 MadeChange |= UpdateNodeTypeFromInst(ResNo, Inst.getResult(ResNo), TP); in ApplyTypeConstraints()
2579 unsigned ResNo = NumResultsToAdd; in ApplyTypeConstraints() local
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H A DDAGISelMatcherGen.cpp1071 for (unsigned ResNo = 0; ResNo < Pattern.getDstPattern()->getNumResults(); in EmitResultCode() local
1072 ++ResNo) { in EmitResultCode()
1073 Results[ResNo] = Ops[Pattern.getDstPattern()->getResultIndex(ResNo)]; in EmitResultCode()
H A DDAGISelMatcher.h531 unsigned ResNo; variable
534 : Matcher(CheckType), Type(type), ResNo(resno) {} in CheckTypeMatcher()
537 unsigned getResNo() const { return ResNo; } in getResNo()
H A DDAGISelMatcher.cpp189 << ResNo << '\n'; in printImpl()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h50 return u.s.ResNo; in getResNo()
71 static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo) { in fromNode() argument
72 return SDDbgOperand(Node, ResNo); in fromNode()
106 unsigned ResNo; ///< Valid for expressions. member
116 u.s.ResNo = R; in SDDbgOperand()
H A DLegalizeTypes.h298 void PromoteIntegerResult(SDNode *N, unsigned ResNo);
357 SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
432 void ExpandIntegerResult(SDNode *N, unsigned ResNo);
536 void SoftenFloatResult(SDNode *N, unsigned ResNo);
621 void ExpandFloatResult(SDNode *N, unsigned ResNo);
693 void PromoteFloatResult(SDNode *N, unsigned ResNo);
737 void SoftPromoteHalfResult(SDNode *N, unsigned ResNo);
784 void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
857 void SplitVectorResult(SDNode *N, unsigned ResNo);
961 void WidenVectorResult(SDNode *N, unsigned ResNo);
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H A DLegalizeFloatTypes.cpp58 dbgs() << "SoftenFloatResult #" << ResNo << ": "; in SoftenFloatResult()
70 R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break; in SoftenFloatResult()
165 SetSoftenedFloat(SDValue(N, ResNo), R); in SoftenFloatResult()
228 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in SoftenFloatRes_MERGE_VALUES()
1276 if (CustomLowerNode(N, N->getValueType(ResNo), true)) in ExpandFloatResult()
1282 dbgs() << "ExpandFloatResult #" << ResNo << ": "; in ExpandFloatResult()
1369 SetExpandedFloat(SDValue(N, ResNo), Lo, Hi); in ExpandFloatResult()
2377 if (CustomLowerNode(N, N->getValueType(ResNo), true)) { in PromoteFloatResult()
2389 dbgs() << "PromoteFloatResult #" << ResNo << ": "; in PromoteFloatResult()
2468 SetPromotedFloat(SDValue(N, ResNo), R); in PromoteFloatResult()
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H A DLegalizeVectorTypes.cpp247 unsigned OtherNo = 1 - ResNo; in ScalarizeVecRes_FFREXP()
257 return SDValue(ScalarNode, ResNo); in ScalarizeVecRes_FFREXP()
323 unsigned OtherNo = 1 - ResNo; in ScalarizeVecRes_OverflowOp()
333 return SDValue(ScalarNode, ResNo); in ScalarizeVecRes_OverflowOp()
1748 Lo = SDValue(LoNode, ResNo); in SplitVecRes_OverflowOp()
1749 Hi = SDValue(HiNode, ResNo); in SplitVecRes_OverflowOp()
1752 unsigned OtherNo = 1 - ResNo; in SplitVecRes_OverflowOp()
2368 unsigned OtherNo = 1 - ResNo; in SplitVecRes_FFREXP()
4688 if (ResNo == 0) { in WidenVecRes_OverflowOp()
4716 unsigned OtherNo = 1 - ResNo; in WidenVecRes_OverflowOp()
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H A DInstrEmitter.h47 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
H A DLegalizeTypesGeneric.cpp34 void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, in ExpandRes_MERGE_VALUES() argument
36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in ExpandRes_MERGE_VALUES()
500 void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, in SplitRes_MERGE_VALUES() argument
502 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in SplitRes_MERGE_VALUES()
H A DInstrEmitter.cpp84 void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, in EmitCopyFromReg() argument
90 SDValue Op(Node, ResNo); in EmitCopyFromReg()
103 MVT VT = Node->getSimpleValueType(ResNo); in EmitCopyFromReg()
113 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
123 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
178 SDValue Op(Node, ResNo); in EmitCopyFromReg()
H A DLegalizeIntegerTypes.cpp46 if (CustomLowerNode(N, N->getValueType(ResNo), true)) { in PromoteIntegerResult()
54 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; in PromoteIntegerResult()
314 SetPromotedInteger(SDValue(N, ResNo), Res); in PromoteIntegerResult()
319 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in PromoteIntRes_MERGE_VALUES()
363 if (ResNo == 1) { in PromoteIntRes_AtomicCmpSwap()
1179 if (ResNo == 1) in PromoteIntRes_SADDSUBO()
1562 if (ResNo == 1) in PromoteIntRes_UADDSUBO()
1594 if (ResNo == 1) in PromoteIntRes_UADDSUBO_CARRY()
1648 if (ResNo == 1) in PromoteIntRes_XMULO()
2596 if (CustomLowerNode(N, N->getValueType(ResNo), true)) in ExpandIntegerResult()
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H A DLegalizeTypes.cpp976 SDValue DAGTypeLegalizer::DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo) { in DisintegrateMERGE_VALUES() argument
978 if (i != ResNo) in DisintegrateMERGE_VALUES()
980 return SDValue(N->getOperand(ResNo)); in DisintegrateMERGE_VALUES()
H A DScheduleDAGSDNodes.cpp125 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency() local
131 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency()
137 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); in CheckForPhysRegDependency()
H A DTargetLowering.cpp5620 unsigned ResNo = 0; // ResNo - The result number of the next output. in ParseConstraints() local
5647 getSimpleValueType(DL, STy->getElementType(ResNo)); in ParseConstraints()
5649 assert(ResNo == 0 && "Asm only has one result!"); in ParseConstraints()
5653 ++ResNo; in ParseConstraints()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h156 unsigned getResNo() const { return ResNo; }
167 return Node == O.Node && ResNo == O.ResNo;
173 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
242 V.ResNo = -1U;
248 V.ResNo = -2U;
1008 return ValueList[ResNo];
1148 : Node(node), ResNo(resno) {
1152 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&
1162 return Node->getValueType(ResNo);
1202 return !Node->hasAnyUseOfValue(ResNo);
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp236 unsigned ResNo = 0; // ResNo - The result number of the next output. in lowerInlineAsm() local
273 TLI->getSimpleValueType(DL, STy->getElementType(ResNo)); in lowerInlineAsm()
275 assert(ResNo == 0 && "Asm only has one result!"); in lowerInlineAsm()
279 ++ResNo; in lowerInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15523 unsigned ResNo = Op0.getResNo(); in PerformExtractEltToVMOVRRD() local
15533 V->getOperand(0).getResNo() == ResNo; in PerformExtractEltToVMOVRRD()
16421 unsigned ResNo = UI.getUse().getResNo(); in CombineVLDDUP() local
16423 if (ResNo == NumVecs) in CombineVLDDUP()
16426 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); in CombineVLDDUP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp16042 unsigned ResNo = User->getOperand(Op).getResNo(); in checkForPhysRegDependency() local
16043 if (User->getOperand(Op)->getValueType(ResNo) != MVT::i1) in checkForPhysRegDependency()
16049 TRI->getMinimalPhysRegClass(PhysReg, Def->getSimpleValueType(ResNo)); in checkForPhysRegDependency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp44261 unsigned ResNo = InputVector.getResNo(); in combineExtractVectorElt() local
44262 auto IsBoolExtract = [&BoolExtracts, &ResNo, &IsVar](SDNode *Use) { in combineExtractVectorElt()
44264 Use->getOperand(0).getResNo() == ResNo && in combineExtractVectorElt()