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Searched refs:RegisterBank (Results 1 – 25 of 60) sorted by relevance

123

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h61 const RegisterBank *RegBank;
67 const RegisterBank &RegBank) in PartialMapping()
389 const RegisterBank **RegBanks;
440 const RegisterBank &getRegBank(unsigned ID) { in getRegBank()
553 const RegisterBank *
585 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank()
606 virtual bool isDivergentRegBank(const RegisterBank *RB) const { in isDivergentRegBank()
622 virtual const RegisterBank &
633 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, in copyCost()
643 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, in cannotCopy()
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H A DRegisterBank.h28 class RegisterBank {
39 constexpr RegisterBank(unsigned ID, const char *Name, in RegisterBank() function
65 bool operator==(const RegisterBank &OtherRB) const;
66 bool operator!=(const RegisterBank &OtherRB) const {
83 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp23 bool RegisterBank::verify(const RegisterBankInfo &RBI, in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
56 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==()
66 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
71 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
H A DRegisterBankInfo.cpp56 RegisterBankInfo::RegisterBankInfo(const RegisterBank **RegBanks, in RegisterBankInfo()
73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
83 const RegisterBank *
114 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints()
142 const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank); in constrainGenericRegister()
198 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
202 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl()
243 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
270 const RegisterBank *RegBank) { in hashPartialMapping()
283 const RegisterBank &RegBank) const { in getPartialMapping()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBanks.td11 def IDRegBank : RegisterBank<"IDBank", [ID]>;
12 def fIDRegBank : RegisterBank<"fIDBank", [fID]>;
13 def vIDRegBank : RegisterBank<"vIDBank", [vID]>;
14 def vfIDRegBank : RegisterBank<"vfIDBank", [vfID]>;
15 def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
H A DSPIRVRegisterBankInfo.h34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp28 class RegisterBank { class
43 RegisterBank(const Record &TheDef, unsigned NumModeIds) in RegisterBank() function in __anona0b0b9ac0111::RegisterBank
111 const std::vector<RegisterBank> &Banks);
113 const std::vector<RegisterBank> &Banks);
115 std::vector<RegisterBank> &Banks);
129 const std::vector<RegisterBank> &Banks) { in emitHeader()
148 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
216 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
298 std::vector<RegisterBank> Banks; in run()
301 RegisterBank Bank(*V, CGH.getNumModeIds()); in run()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBanks.td15 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
17 def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
19 def VECRegBank : RegisterBank<"VEC", [VSRC]>;
21 def CRRegBank : RegisterBank<"CR", [CRRC]>;
H A DPPCRegisterBankInfo.cpp32 const RegisterBank &
228 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping()
229 const RegisterBank &SrcRB = SrcIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBanks.td9 def SGPRRegBank : RegisterBank<"SGPR",
13 def VGPRRegBank : RegisterBank<"VGPR",
18 def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
20 def AGPRRegBank : RegisterBank <"AGPR",
H A DAMDGPURegisterBankInfo.h168 bool isDivergentRegBank(const RegisterBank *RB) const override;
170 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
174 const RegisterBank *CurBank = nullptr) const override;
176 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
H A DAMDGPURegisterBankInfo.cpp103 const RegisterBank *NewBank;
286 const RegisterBank &
1064 const RegisterBank *DstBank = in applyMappingLoad()
1467 const RegisterBank *DstBank = in applyMappingBFE()
1622 const RegisterBank &DstBank = in applyMappingMAD_64_32()
1930 const RegisterBank &IdxBank = in foldExtractEltToCmpSelect()
1945 const RegisterBank &DstBank = in foldExtractEltToCmpSelect()
1947 const RegisterBank &SrcBank = in foldExtractEltToCmpSelect()
1950 const RegisterBank &CCBank = in foldExtractEltToCmpSelect()
2028 const RegisterBank &IdxBank = in foldInsertEltToCmpSelect()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.h66 unsigned ValLength, const RegisterBank &RB);
142 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
145 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
H A DAArch64RegisterBankInfo.cpp56 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
66 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
218 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost()
219 const RegisterBank &B, in copyCost()
239 const RegisterBank &
716 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
717 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
741 const RegisterBank &DstRB = in getInstrMapping()
743 const RegisterBank &SrcRB = in getInstrMapping()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBanks.td13 def GPRBRegBank : RegisterBank<"GPRB", [GPR]>;
16 def FPRBRegBank : RegisterBank<"FPRB", [FPR64]>;
19 def VRBRegBank : RegisterBank<"VRB", [VRM8]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterBanks.td13 def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>;
16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
19 def CCRegBank : RegisterBank<"CC", [CCR]>;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h31 class RegisterBank; variable
46 const RegisterBank *RegBank;
53 using Name2RegBankMap = StringMap<const RegisterBank *>;
151 const RegisterBank *getRegBank(StringRef Name);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBanks.td12 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
14 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
12 class RegisterBank<string name, list<RegisterClass> classes> {
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBanks.td12 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
H A DARMRegisterBankInfo.h35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBanks.td13 def GPRRegBank : RegisterBank<"GPR", [GR64]>;
16 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp206 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
255 const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank); in selectDebugInstr()
559 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
768 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
769 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
897 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
898 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1135 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectUAddSub()
1419 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues()
1488 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCSEInfo.h166 class RegisterBank; variable
183 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kRegisterBankInfo.h38 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,

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