| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterPressure.cpp | 363 Register RegUnit = Pair.RegUnit; in initLiveThru() local
373 return Other.RegUnit == RegUnit; in getRegLanes()
382 Register RegUnit = Pair.RegUnit; in addRegLanes() local
385 return Other.RegUnit == RegUnit; in addRegLanes()
397 return Other.RegUnit == RegUnit; in setRegZero()
408 Register RegUnit = Pair.RegUnit; in removeRegLanes() local
411 return Other.RegUnit == RegUnit; in removeRegLanes()
607 Register RegUnit = I->RegUnit; in adjustLaneLiveness() local
633 Register RegUnit = P.RegUnit; in adjustLaneLiveness() local
716 Register RegUnit = Pair.RegUnit; in discoverLiveInOrOut() local
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| H A D | LiveRegMatrix.cpp | 179 MCRegister RegUnit) { in query() argument
180 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
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| H A D | MachineCopyPropagation.cpp | 254 MachineInstr *findCopyForUnit(MCRegister RegUnit, in findCopyForUnit() argument
257 auto CI = Copies.find(RegUnit); in findCopyForUnit()
265 MachineInstr *findCopyDefViaUnit(MCRegister RegUnit, in findCopyDefViaUnit() argument
267 auto CI = Copies.find(RegUnit); in findCopyDefViaUnit()
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| H A D | MachineTraceMetrics.cpp | 1148 TBI.LiveIns.push_back(LiveInReg(RU.RegUnit, RU.Cycle)); in computeInstrHeights()
1149 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RU.RegUnit, MTM.TRI) << '@' in computeInstrHeights()
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| H A D | MachinePipeliner.cpp | 1252 auto Reg = Use.RegUnit; in computeLiveIn()
1339 UpdateTargetRegs(Use.RegUnit); in computeLastUses()
1350 auto Reg = Use.RegUnit; in computeLastUses()
1443 InsertReg(LiveRegSets[Iter], Def.RegUnit); in computeMaxSetPressure()
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| H A D | MachineScheduler.cpp | 1325 Register Reg = P.RegUnit; in updatePressureDiffs()
1550 Register Reg = P.RegUnit; in computeCyclicCriticalPath()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 39 Register RegUnit; ///< Virtual register or register unit. member
42 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
43 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
159 void addPressureChange(Register RegUnit, bool IsDec,
307 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in insert()
320 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in erase()
542 void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
544 void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
565 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
566 LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
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| H A D | MachineTraceMetrics.h | 75 unsigned RegUnit; member
80 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
82 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
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| H A D | MachineRegisterInfo.h | 654 PSetIterator getPressureSets(Register RegUnit) const;
1240 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1242 if (RegUnit.isVirtual()) { in PSetIterator()
1243 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1247 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1248 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1269 MachineRegisterInfo::getPressureSets(Register RegUnit) const { in getPressureSets() argument
1270 return PSetIterator(RegUnit, this); in getPressureSets()
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| H A D | ScheduleDAGInstrs.h | 80 unsigned RegUnit; member
83 : SU(su), OpIdx(op), RegUnit(R) {} in PhysRegSUOper()
85 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
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| H A D | TargetRegisterInfo.h | 437 bool hasRegUnit(MCRegister Reg, Register RegUnit) const { in hasRegUnit() argument
439 if (Register(Unit) == RegUnit) in hasRegUnit()
864 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
884 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
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| H A D | LiveRegMatrix.h | 153 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
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| /freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 517 struct RegUnit { struct
535 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit() argument
586 SmallVector<RegUnit, 8> RegUnits;
724 RegUnit &RU = RegUnits.back();
752 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
753 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
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| H A D | CodeGenRegisters.cpp | 590 for (unsigned RegUnit : RegUnits) { in getWeight() local
591 Weight += RegBank.getRegUnit(RegUnit).Weight; in getWeight()
1136 const RegUnit &RU = RegBank.getRegUnit(*UnitI); in buildRegUnitSet()
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| H A D | RegisterInfoEmitter.cpp | 251 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); in EmitRegUnitPressure()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 710 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
711 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
712 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
713 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 324 LiveRange &RegUnit = LIS->getRegUnit(Unit); in optimizeElseBranch() local
325 if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx))) in optimizeElseBranch()
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| H A D | SIMachineScheduler.h | 468 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
476 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
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| H A D | GCNRegPressure.cpp | 182 return RM.RegUnit == Reg; in collectVirtualRegUses()
316 LaneBitmask &LiveMask = LiveRegs[U.RegUnit]; in recede()
319 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI); in recede()
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| H A D | SIRegisterInfo.h | 329 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
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| H A D | SIMachineScheduler.cpp | 332 if (RegMaskPair.RegUnit.isVirtual()) in initRegPressure()
333 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
359 Register Reg = RegMaskPair.RegUnit; in initRegPressure()
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| H A D | SIRegisterInfo.cpp | 3070 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
3073 if (RegPressureIgnoredUnits[RegUnit]) in getRegUnitPressureSets()
3076 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfDebug.cpp | 718 for (auto &RegUnit : ClobberedRegUnits) in interpretValues() local
719 if (TRI.hasRegUnit(Reg, RegUnit)) in interpretValues()
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