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Searched refs:RegType (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td6126 [(set (AccumType RegType:$dst),
6127 (OpNode (AccumType RegType:$Rd),
6149 [(set (AccumType RegType:$dst),
8581 …: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, [(set (AccumType RegType:…
8604 RegType, RegType, V128, VectorIndexS,
8606 [(set (AccumType RegType:$dst),
8709 RegType, RegType, RegType_lo, VectorIndexB,
8747 BaseSIMDIndexedTied<Q, U, 0b0, size, opc, RegType, RegType, V128,
8749 [(set (AccumType RegType:$dst),
8783 BaseSIMDIndexedTied<Q, U, 0, sz, opc, RegType, RegType, RegType_lo,
[all …]
H A DAArch64FrameLowering.cpp2757 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
H A DAArch64InstrInfo.td1297 string rhs_kind, RegisterOperand RegType,
1300 lhs_kind, rhs_kind, RegType, AccumType,
1302 let Pattern = [(set (AccumType RegType:$dst),
1303 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd),
1307 (InputType RegType:$Rn))))];
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7313 MVT RegType = TLI->getPreferredSwitchConditionType(Context, OldVT); in optimizeSwitchType() local
7314 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType()
7333 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3559 char RegType = RegTypes[RegNo / 8]; in getRegForInlineAsmConstraint() local
3561 char Tmp[] = {'{', RegType, RegIndex, '}', 0}; in getRegForInlineAsmConstraint()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td246 // RegType - Specify the list ValueType of the registers in this register