Home
last modified time | relevance | path

Searched refs:RegSize (Results 1 – 25 of 33) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp153 if (AArch64_AM::isLogicalImmediate(UImm, RegSize)) in splitBitmaskImm()
158 AArch64_IMM::expandMOVImm(UImm, RegSize, Insn); in splitBitmaskImm()
203 [Opc](T Imm, unsigned RegSize, T &Imm0, in visitAND()
205 if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1)) in visitAND()
339 AArch64_IMM::expandMOVImm(Imm, RegSize, Insn); in splitAddSubImm()
376 if (splitAddSubImm(Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
411 &MRI = MRI](T Imm, unsigned RegSize, T &Imm0, in visitADDSSUBS()
414 if (splitAddSubImm(Imm, RegSize, Imm0, Imm1)) in visitADDSSUBS()
488 unsigned RegSize = sizeof(T) * 8; in splitTwoPartImm() local
489 assert((RegSize == 32 || RegSize == 64) && in splitTwoPartImm()
[all …]
H A DAArch64FastISel.cpp1670 unsigned RegSize; in emitLogicalOp_ri() local
1681 RegSize = 32; in emitLogicalOp_ri()
1687 RegSize = 64; in emitLogicalOp_ri()
1691 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1696 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4102 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4149 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4205 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4253 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4321 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
[all …]
H A DAArch64FrameLowering.cpp3322 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
3325 SVECSStackSize += RegSize; in determineCalleeSaves()
3327 CSStackSize += RegSize; in determineCalleeSaves()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DInfoByHwMode.cpp121 RegSize = R->getValueAsInt("RegSize"); in RegSizeInfo()
127 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
128 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
132 return RegSize <= I.RegSize && in isSubClassOf()
138 OS << "[R=" << RegSize << ",S=" << SpillSize in writeToStream()
H A DInfoByHwMode.h185 unsigned RegSize; member
193 return std::tie(RegSize, SpillSize, SpillAlignment) ==
194 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
H A DRegisterInfoEmitter.cpp1065 uint32_t RegSize = 0; in runMCDesc() local
1067 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1071 << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1287 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFrameLowering.cpp127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
128 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
H A DMipsCallLowering.cpp413 unsigned RegSize = 4; in lowerFormalArguments() local
415 VaArgOffset = alignTo(CCInfo.getStackSize(), RegSize); in lowerFormalArguments()
419 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
423 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
426 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
428 LLT RegTy = LLT::scalar(RegSize * 8); in lowerFormalArguments()
431 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
437 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize)); in lowerFormalArguments()
H A DMipsSEFrameLowering.cpp78 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80 unsigned MFLoOpc, unsigned RegSize);
198 unsigned RegSize) { in expandLoadACC() argument
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC() argument
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp138 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
144 SmallBitVector Coverage(RegSize, false); in addMachineReg()
155 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
179 if (CurPos < RegSize) in addMachineReg()
181 -1, RegSize - CurPos, "no DWARF register encoding")); in addMachineReg()
291 unsigned RegSize = 0; in addMachineRegExpression() local
293 RegSize += Reg.SubRegSize; in addMachineRegExpression()
297 if (RegSize > FragmentInfo->SizeInBits) in addMachineRegExpression()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp179 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY() local
180 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16)) in INITIALIZE_PASS_DEPENDENCY()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && in processLogicalImmediate()
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
221 unsigned Size = RegSize; in processLogicalImmediate()
/freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/
H A DX86.h240 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
246 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
794 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
800 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
805 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, in validateGlobalRegisterVariable()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DAArch64.cpp565 int RegSize = IsIndirect ? 8 : TySize.getQuantity(); in EmitAAPCSVAArg() local
571 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
577 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
618 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
H A DPPC.cpp454 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
456 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
459 DirectTy, RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h241 unsigned RegSize, SpillSize, SpillAlignment; member
287 return TypeSize::getFixed(getRegClassInfo(RC).RegSize); in getRegSizeInBits()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp927 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
929 explicit operator bool() const { return RegSize; } in operator bool()
931 unsigned RegSize = 0; member
977 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
979 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
981 if (And.RegSize == 64) { in convertToThreeAddress()
H A DSystemZFrameLowering.cpp1034 unsigned RegSize = 8; in assignCalleeSavedSpillSlots() local
1035 int FrameIdx = MFFrame.CreateFixedSpillStackObject(RegSize, Offset); in assignCalleeSavedSpillSlots()
1496 const unsigned RegSize = MF.getDataLayout().getPointerSize(); in determineFrameLayout() local
1501 MFFrame.CreateFixedSpillStackObject(RegSize, Offset - StackSize)); in determineFrameLayout()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp496 unsigned RegSize = RegTy.getSizeInBits(); in extractParts() local
498 unsigned NumParts = RegSize / MainSize; in extractParts()
499 unsigned LeftoverSize = RegSize - NumParts * MainSize; in extractParts()
574 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; in extractParts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
430 CSStackSize += RegSize; in determineCalleeSaves()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp558 int RegSize; in sizeOfSPAdjustment() local
561 RegSize = 8; in sizeOfSPAdjustment()
565 RegSize = 4; in sizeOfSPAdjustment()
578 count += RegSize; in sizeOfSPAdjustment()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A DTargetInfo.h1152 unsigned RegSize, in validateGlobalRegisterVariable() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp326 unsigned RegSize = Ty.getSizeInBits(); in isLoadStoreSizeLegal() local
336 if (Ty.isVector() && MemSize != RegSize) in isLoadStoreSizeLegal()
348 if (MemSize != RegSize && RegSize != 32) in isLoadStoreSizeLegal()
375 assert(RegSize >= MemSize); in isLoadStoreSizeLegal()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp857 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() local
858 assert(RegSize == 32 || RegSize == 64 || in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp4528 unsigned RegSize = Ty.getSizeInBits(); in emitTST() local
4529 bool Is32Bit = (RegSize == 32); in emitTST()
4538 if (AArch64_AM::isLogicalImmediate(Imm, RegSize)) { in emitTST()
4540 TstMI.addImm(AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitTST()

12