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Searched refs:RegReg (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.h24 RegReg, // SH1ADD/SH2ADD/SH3ADD enumerator
H A DRISCVMatInt.cpp502 return RISCVMatInt::RegReg; in getOpndKind()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp336 RegReg, enumerator
398 struct RegRegOp RegReg; member
439 case KindTy::RegReg: in RISCVOperand()
440 RegReg = o.RegReg; in RISCVOperand()
1067 case KindTy::RegReg: in print()
1068 OS << "<RegReg: Reg1 " << RegName(RegReg.Reg1); in print()
1069 OS << " Reg2 " << RegName(RegReg.Reg2); in print()
1157 Op->RegReg.Reg1 = Reg1No; in createRegReg()
1158 Op->RegReg.Reg2 = Reg2No; in createRegReg()
1241 Inst.addOperand(MCOperand::createReg(RegReg.Reg1)); in addRegRegOperands()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp937 case RISCVMatInt::RegReg: in materializeImm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXCV.td510 let Name = "RegReg";
H A DRISCVInstrInfo.cpp853 case RISCVMatInt::RegReg: in movImm()
H A DRISCVISelDAGToDAG.cpp190 case RISCVMatInt::RegReg: in selectImmSeq()