| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.cpp | 117 const X86FoldTableEntry *Data = llvm::lower_bound(Table, RegOp); in lookupFoldTableImpl()
118 if (Data != Table.end() && Data->KeyOp == RegOp && in lookupFoldTableImpl()
125 llvm::lookupTwoAddrFoldTable(unsigned RegOp) { in lookupTwoAddrFoldTable() argument
126 return lookupFoldTableImpl(Table2Addr, RegOp); in lookupTwoAddrFoldTable()
130 llvm::lookupFoldTable(unsigned RegOp, unsigned OpNum) { in lookupFoldTable() argument
145 return lookupFoldTableImpl(FoldTable, RegOp); in lookupFoldTable()
233 unsigned RegOp = Reg2Bcst.KeyOp; in X86BroadcastFoldTable() local
243 unsigned RegOp = Reg2Bcst.KeyOp; in X86BroadcastFoldTable() local
254 unsigned RegOp = Reg2Bcst.KeyOp; in X86BroadcastFoldTable() local
264 unsigned RegOp = Reg2Bcst.KeyOp; in X86BroadcastFoldTable() local
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| H A D | X86InstrFoldTables.h | 41 const X86FoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
45 const X86FoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 214 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
215 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
249 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
255 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
265 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
276 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
285 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVDuplicatesTracker.cpp | 57 MachineOperand *RegOp = &MRI.getVRegDef(Op.getReg())->getOperand(0); in buildDepsGraph() local
59 Reg2Entry.count(RegOp)); in buildDepsGraph()
60 if (Reg2Entry.count(RegOp)) in buildDepsGraph()
61 E->addDep(Reg2Entry[RegOp]); in buildDepsGraph()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 557 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
558 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
559 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
560 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
561 getUndefRegState(RegOp.isUndef()) | in getRegState()
562 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
563 getDebugRegState(RegOp.isDebug()) | in getRegState()
564 getRenamableRegState(RegOp.getReg().isPhysical() && in getRegState()
565 RegOp.isRenamable()); in getRegState()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFInstPrinter.cpp | 72 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
76 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
77 O << getRegisterName(RegOp.getReg()); in printMemOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAsmPrinter.cpp | 130 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
131 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
133 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCCodeEmitter.cpp | 140 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
143 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
147 switch (RegOp.getReg()) { in encodeMemri()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 543 unsigned RegOp = OpNum; in PrintAsmOperand() local
549 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
552 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
555 RegOp = OpNum + 1; in PrintAsmOperand()
557 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
559 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1638 const MachineOperand *RegOp = nullptr; in isOMod() local
1644 RegOp = Src1; in isOMod()
1647 RegOp = Src0; in isOMod()
1659 return std::pair(RegOp, OMod); in isOMod()
1697 const MachineOperand *RegOp; in tryFoldOMod() local
1699 std::tie(RegOp, OMod) = isOMod(MI); in tryFoldOMod()
1700 if (OMod == SIOutMods::NONE || !RegOp->isReg() || in tryFoldOMod()
1701 RegOp->getSubReg() != AMDGPU::NoSubRegister || in tryFoldOMod()
1702 !MRI->hasOneNonDBGUser(RegOp->getReg())) in tryFoldOMod()
1705 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod()
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 1834 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfBlock() local
1835 ArrayRef<MachineOperand> Cond(RegOp); in createIfBlock()
2291 MachineOperand RegOp = in createIfRegion() local
2293 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
2350 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
2351 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
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| H A D | SIInstrInfo.cpp | 1281 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1282 RegOp.setImplicit(false); in insertVectorSelect()
1285 .add(RegOp); in insertVectorSelect()
1296 RegOp.setImplicit(false); in insertVectorSelect()
1299 .add(RegOp); in insertVectorSelect()
2691 Register Reg = RegOp.getReg(); in swapRegAndNonRegOperand()
2693 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand()
2694 bool IsDead = RegOp.isDead(); in swapRegAndNonRegOperand()
2695 bool IsUndef = RegOp.isUndef(); in swapRegAndNonRegOperand()
2696 bool IsDebug = RegOp.isDebug(); in swapRegAndNonRegOperand()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1081 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrix() local
1082 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrix()
1084 printRegName(O, RegOp.getReg()); in printMatrix()
1112 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTileVector() local
1113 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTileVector()
1114 StringRef RegName = getRegisterName(RegOp.getReg()); in printMatrixTileVector()
1125 const MCOperand &RegOp = MI->getOperand(OpNum); in printMatrixTile() local
1126 assert(RegOp.isReg() && "Unexpected operand type!"); in printMatrixTile()
1127 printRegName(O, RegOp.getReg()); in printMatrixTile()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 88 struct RegOp { struct
99 RegOp Reg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86EncodingOptimization.cpp | 341 unsigned RegOp = IsStore ? 0 : 5; in optimizeMOV() local
344 unsigned Reg = MI.getOperand(RegOp).getReg(); in optimizeMOV()
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| H A D | X86MCCodeEmitter.cpp | 1754 unsigned RegOp = CurOp++; in encodeInstruction() local
1761 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), in encodeInstruction()
1767 unsigned RegOp = CurOp++; in encodeInstruction() local
1771 emitRegModRMByte(MI.getOperand(RegOp), 0, CB); in encodeInstruction()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
| H A D | XtensaAsmParser.cpp | 98 struct RegOp { struct
109 RegOp Reg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 355 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs() local
356 if (!RegOp.isVirtual()) in collectUnprimedAccPHIs()
358 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs()
399 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs() local
400 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 49 struct RegOp { struct
84 struct RegOp Reg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 429 MachineOperand &RegOp = PI.getOperand(i); in preprocessPhiNodes() local
430 if (RegOp.getSubReg() == 0) in preprocessPhiNodes()
440 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
441 RegOp.getSubReg()); in preprocessPhiNodes()
443 RegOp.setReg(NewReg); in preprocessPhiNodes()
444 RegOp.setSubReg(0); in preprocessPhiNodes()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 120 struct RegOp { struct
137 struct RegOp Reg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 413 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; in PrintAsmOperand() local
414 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
416 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 164 struct RegOp { struct in __anonb17833500111::LoongArchOperand
175 struct RegOp Reg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 175 struct RegOp { struct in __anonb0359a6c0211::VEOperand
205 struct RegOp Reg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 110 struct RegOp { struct in __anon2dbeb9140111::SystemZOperand
140 RegOp Reg;
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