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Searched refs:RegLo (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp468 Register RegLo = VA.getLocReg(); in LowerReturn() local
469 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerReturn()
470 Register RegHi = RegLo + 1; in LowerReturn()
472 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn()
474 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); in LowerReturn()
585 Register RegLo = VA.getLocReg(); in LowerCall() local
586 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall()
588 if (RegLo == CSKY::R3) { in LowerCall()
598 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerCall()
599 Register RegHigh = RegLo + 1; in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2713 int64_t RegLo, RegHi; in ParseRegRange() local
2720 if (!parseExpr(RegLo)) in ParseRegRange()
2728 RegHi = RegLo; in ParseRegRange()
2734 if (!isUInt<32>(RegLo)) { in ParseRegRange()
2744 if (RegLo > RegHi) { in ParseRegRange()
2749 Num = static_cast<unsigned>(RegLo); in ParseRegRange()
2750 RegWidth = 32 * ((RegHi - RegLo) + 1); in ParseRegRange()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1914 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
1916 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp2394 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
2425 BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo).addReg(RegLo).add(OpLo)); in expandPostRAPseudo()
H A DSIISelLowering.cpp5003 Register RegLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
5004 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B32), RegLo) in EmitInstrWithCustomInserter()
5009 .addReg(RegLo) in EmitInstrWithCustomInserter()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp18400 Register RegLo = VA.getLocReg(); in LowerCall() local
18401 RegsToPass.push_back(std::make_pair(RegLo, Lo)); in LowerCall()
18674 Register RegLo = VA.getLocReg(); in LowerReturn() local
18677 if (STI.isRegisterReservedByUser(RegLo) || in LowerReturn()
18683 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); in LowerReturn()
18685 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4223 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local
4225 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32); in LowerFormalArguments_32SVR4()