| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 113 unsigned &RegKind);
1172 unsigned RegKind; in parseOperand() local
1265 unsigned RegKind; in parseSparcAsmOperand() local
1332 RegKind = SparcOperand::rk_None; in matchRegisterName()
1339 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1345 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1436 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1443 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1449 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1455 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 67 enum class RegKind { enum
277 template <RegKind RK>
380 RegKind Kind;
1237 RegKind RK; in isSVEPredicateAsCounterReg()
1255 RegKind RK; in isSVEVectorReg()
2258 assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector || in CreateVectorReg()
2683 case RegKind::Matrix: in parseVectorKind()
2970 case RegKind::Scalar: in getNumRegsForRegKind()
2974 case RegKind::Matrix: in getNumRegsForRegKind()
4171 template <RegKind RK>
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 123 unsigned RegKind : 4; member
189 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
194 Op->Mem.RegKind = RegKind; in createMem()
227 bool isReg(RegisterKind RegKind) const { in isReg()
228 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
268 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
269 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
277 bool isMemDisp12Len4(RegisterKind RegKind) const { in isMemDisp12Len4()
280 bool isMemDisp12Len8(RegisterKind RegKind) const { in isMemDisp12Len8()
437 RegisterKind RegKind);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1271 switch (RegKind) { in usesRegister()
2547 switch (RegKind) { in AddNextRegisterToList()
2671 assert(isRegularReg(RegKind)); in getRegularReg()
2674 if (RegKind == IS_SGPR || RegKind == IS_TTMP) { in getRegularReg()
2686 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg()
2762 RegKind = IS_SPECIAL; in ParseSpecialReg()
2785 RegKind = RI->Kind; in ParseRegularReg()
2848 if (NextRegKind != RegKind) { in ParseRegList()
2861 if (isRegularReg(RegKind)) in ParseRegList()
2918 switch (RegKind) { in getGprCountSymbolName()
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| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/ABI/X86/ |
| H A D | ABIX86.cpp | 50 enum RegKind { enum
64 RegKind subreg_kind;
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| /freebsd-14.2/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMWinEHPrinter.cpp | 885 int RegKind = (OC[Offset + 2] & 0xC0) >> 6; in opcode_save_any_reg() local
892 if (!Writeback && !Paired && RegKind != 2) in opcode_save_any_reg()
906 if (RegKind == 0) in opcode_save_any_reg()
908 if ((OC[Offset + 1] & 0x80) == 0x80 || RegKind == 3 || Reg > MaxReg) { in opcode_save_any_reg()
927 if (RegKind == 1) { in opcode_save_any_reg()
929 } else if (RegKind == 2) { in opcode_save_any_reg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 570 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
580 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
906 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
945 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
1008 let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";
1009 let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "
1040 "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
1166 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
1168 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
1265 "isTypedVectorListMultiple<RegKind::SVEDataVector, " # NumRegs # ", 0, "
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.h | 31 enum RegKind { enum
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 447 bool validateMSAIndex(int Val, int RegKind);
813 enum RegKind { enum in __anonb0f64e280211::MipsOperand
871 RegKind Kind; /// Bitfield of the kinds it could possibly be
901 RegKind RegKind, in CreateReg() argument
908 Op->RegIdx.Kind = RegKind; in CreateReg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorize.cpp | 4838 TargetTransformInfo::RegisterKind RegKind = in getMaximizedVFForTarget() local
4844 (TTI.shouldMaximizeVectorBandwidth(RegKind) || in getMaximizedVFForTarget()
7287 TargetTransformInfo::RegisterKind RegKind = in determineVPlanVF() local
7292 TypeSize RegSize = TTI.getRegisterBitWidth(RegKind); in determineVPlanVF()
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