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Searched refs:RegClasses (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp990 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
1015 for (auto &RC : RegClasses) { in computeSubClasses()
1031 for (auto &RC : RegClasses) in computeSubClasses()
1059 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs()
1069 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs()
1290 for (auto &RC : RegClasses) in CodeGenRegBank()
1355 return &RegClasses.back(); in getOrCreateSubClass()
2229 assert(!RegClasses.empty()); in inferCommonSubClass()
2232 for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end()); in inferCommonSubClass()
2388 assert(!RegClasses.empty()); in computeInferredRegisterClasses()
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H A DCodeGenTarget.cpp319 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace() local
320 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; in getRegNamespace()
382 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg() local
386 for (CodeGenRegisterClass &RC : RegClasses) { in getSuperRegForSubReg()
H A DCodeGenRegisters.h589 std::list<CodeGenRegisterClass> RegClasses; variable
634 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
755 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
758 return RegClasses; in getRegClasses()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td491 // a list of register classes (see field `RegClasses`). An empty list of
495 // A register R can be renamed if its register class appears in the `RegClasses`
500 // However, V is only renamed if its register class is part of `RegClasses`.
511 // register class that is in `RegClasses`.
553 list<RegisterClass> RegClasses = Classes;