Searched refs:RegClassIDs (Results 1 – 2 of 2) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 359 SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
1374 static const unsigned RegClassIDs[] = { in createDTuple() local
1379 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1383 static const unsigned RegClassIDs[] = { in createQTuple() local
1388 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1392 static const unsigned RegClassIDs[] = {AArch64::ZPR2RegClassID, in createZTuple() local
1398 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1406 static const unsigned RegClassIDs[] = {AArch64::ZPR2Mul2RegClassID, 0, in createZMulTuple() local
1410 return createTuple(Regs, RegClassIDs, SubRegs); in createZMulTuple()
1414 const unsigned RegClassIDs[], in createTuple() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 689 const unsigned RegClassIDs[], in createTuple() argument
697 auto *DesiredClass = TRI->getRegClass(RegClassIDs[NumRegs - 2]); in createTuple()
709 static const unsigned RegClassIDs[] = { in createDTuple() local
713 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createDTuple()
718 static const unsigned RegClassIDs[] = { in createQTuple() local
722 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createQTuple()
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