| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 104 unsigned RegClassID; in Select() local
111 RegClassID = R600::R600_Reg64RegClassID; in Select()
115 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
117 RegClassID = R600::R600_Reg128RegClassID; in Select()
122 SelectBuildVector(N, RegClassID); in Select()
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| H A D | AMDGPUISelDAGToDAG.h | 104 void SelectBuildVector(SDNode *N, unsigned RegClassID);
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| H A D | AMDGPUISelDAGToDAG.cpp | 434 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
439 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
456 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
559 unsigned RegClassID = in Select() local
561 SelectBuildVector(N, RegClassID); in Select()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRVVInitUndef.cpp | 117 static unsigned getUndefInitOpcode(unsigned RegClassID) { in getUndefInitOpcode() argument
118 switch (RegClassID) { in getUndefInitOpcode()
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| H A D | RISCVISelDAGToDAG.cpp | 252 unsigned RegClassID; in createTuple() local
264 RegClassID = M1TupleRegClassIDs[NF - 2]; in createTuple()
270 RegClassID = M2TupleRegClassIDs[NF - 2]; in createTuple()
276 RegClassID = RISCV::VRN2M4RegClassID; in createTuple()
283 Ops.push_back(CurDAG.getTargetConstant(RegClassID, DL, MVT::i32)); in createTuple()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.h | 113 const char* getRegClassName(unsigned RegClassID) const;
116 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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| H A D | AMDGPUDisassembler.cpp | 134 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
1249 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
1251 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1270 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
1272 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
1274 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1635 switch (RegClassID) { in GetSIDIForRegClass()
1669 int RegClassID = -1; in VerifyAndAdjustOperands() local
1690 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1691 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1697 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1699 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1701 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
1708 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
4738 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, in parseSEHRegisterNumber() argument
4749 if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) { in parseSEHRegisterNumber()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 517 unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass; in scavengeRegister() local
518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| H A D | AArch64RegisterInfo.td | 674 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
903 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
942 # RegClass # "RegClassID>";
1086 # RegClassSuffix # "RegClassID>";
1127 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1518 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1659 # EltSize # ", AArch64::" # RC # "RegClassID>";
1686 # EltSize # ", AArch64::" # RC # "RegClassID>";
1721 # EltSize # ", AArch64::" # RC # "RegClassID>";
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 77 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { in isMemOperand() argument
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 1275 unsigned RegClassID; in convertVRToVRMx() local
1277 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1279 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1281 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1285 &RISCVMCRegisterClasses[RegClassID]); in convertVRToVRMx()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1938 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1945 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1383 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1385 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1388 template <unsigned RegClassID, int ExtWidth>
1393 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 1840 template<unsigned Bits, unsigned RegClassID>
1843 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()
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