| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 473 if (RegA == RegB) in regsAreCompatible()
475 if (!RegA || !RegB) in regsAreCompatible()
749 DstRegMap.erase(RegB); in convertInstTo3Addr()
1489 Register RegB = 0; in processTiedPairs() local
1503 if (RegA == RegB) { in processTiedPairs()
1529 MIB.addReg(RegB, 0, SubRegB); in processTiedPairs()
1598 if (MO.getReg() == RegB) { in processTiedPairs()
1651 if (MO.getReg() == RegB) { in processTiedPairs()
1671 Register RegB = TO.first; in processStatepoint() local
1685 if (RegA == RegB) in processStatepoint()
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| H A D | ImplicitNullChecks.cpp | 291 Register RegB = MOB.getReg(); in canReorder() local
293 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
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| H A D | TargetInstrInfo.cpp | 1094 Register RegB = OpB.getReg(); in reassociateOps() local
1101 if (RegB.isVirtual()) in reassociateOps()
1102 MRI.constrainRegClass(RegB, RC); in reassociateOps()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 473 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
474 return isSuperRegister(RegB, RegA); in isSubRegister()
478 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
481 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
482 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
487 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
488 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
493 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
494 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
498 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 135 bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const { in regsOverlap()
139 auto RangeB = regunits(RegB); in regsOverlap()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 428 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap() argument
429 if (RegA == RegB) in regsOverlap()
431 if (RegA.isPhysical() && RegB.isPhysical()) in regsOverlap()
432 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg()); in regsOverlap()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 669 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister() argument
670 return TRI.isSuperOrSubRegisterEq(RegA, RegB); in isArgumentRegister()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 500 Register RegB = Root.getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
501 MachineInstr *Prev = MRI->getUniqueVRegDef(RegB); in getFMAPatterns()
846 RegA21, RegB; in reassociateFMA() local
851 GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB); in reassociateFMA()
1001 .addReg(RegB, getKillRegState(RegB)) in reassociateFMA()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2224 for (auto &RegB : UsesB) { in isDependent() local
2226 if (RegA == RegB) in isDependent()
2229 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB)) in isDependent()
2232 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA)) in isDependent()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6889 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genSubAdd2SubSub() local
6907 .addReg(RegB, getKillRegState(RegBIsKill)); in genSubAdd2SubSub()
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