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Searched refs:Reg64 (Results 1 – 3 of 3) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp232 const Register Reg64 = MI->getOperand(0).getReg(); in expandLoadStackGuard() local
233 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard()
241 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
244 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64) in expandLoadStackGuard()
245 .addReg(Reg64) in expandLoadStackGuard()
255 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0); in expandLoadStackGuard()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td566 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
574 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
592 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
598 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
604 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
610 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
H A DAArch64FastISel.cpp1877 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad() local
1879 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1883 ResultReg = Reg64; in emitLoad()
4014 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext() local
4016 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
4020 ResultReg = Reg64; in emiti1Ext()
4534 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad() local
4536 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4540 Reg = Reg64; in optimizeIntExtLoad()