| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 701 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
703 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
706 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
709 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
712 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
715 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
720 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
726 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
729 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
732 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && in generateCompactUnwindEncoding()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 1102 Register Reg1, Reg2; in parseAddress() local
1146 if (parseAddressRegister(Reg2)) in parseAddress()
1148 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1154 if (parseAddressRegister(Reg2)) in parseAddress()
1156 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1172 if (parseAddressRegister(Reg2)) in parseAddress()
1174 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1184 if (parseAddressRegister(Reg2)) in parseAddress()
1186 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1495 Register Reg1, Reg2; in parseOperand() local
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| H A D | MipsAsmPrinter.cpp | 837 unsigned Reg2) { in EmitInstrRegReg() argument
846 Reg1 = Reg2; in EmitInstrRegReg()
847 Reg2 = Temp; in EmitInstrRegReg()
851 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
857 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
861 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
868 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
872 Reg1 = Reg2; in EmitMovFPIntPair()
873 Reg2 = temp; in EmitMovFPIntPair()
876 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
|
| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
|
| H A D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
|
| H A D | Mips16InstrInfo.h | 121 unsigned Reg1, unsigned Reg2) const;
|
| H A D | MipsTargetStreamer.h | 133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 204 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
207 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitStore()
209 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitStore()
234 MIB.addReg(Reg2); in emitStore()
245 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
248 const bool IsPaired = Reg2 != AArch64::NoRegister; in emitLoad()
250 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitLoad()
275 MIB.addReg(Reg2, getDefRegState(true)); in emitLoad()
|
| H A D | AArch64FrameLowering.cpp | 2713 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
2847 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2853 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2857 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2995 MIB.addReg(RPI.Reg2); in spillCalleeSavedRegisters()
3007 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
3063 std::swap(Reg1, Reg2); in spillCalleeSavedRegisters()
3071 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
3072 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)); in spillCalleeSavedRegisters()
3113 unsigned Reg2 = RPI.Reg2; in restoreCalleeSavedRegisters() local
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
|
| H A D | PPCVSXSwapRemoval.cpp | 899 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
900 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 105 bool contains(Register Reg1, Register Reg2) const { in contains() argument
108 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
110 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 83 unsigned Reg2);
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
454 .addReg(Reg2) in createRegSequence()
|
| H A D | Thumb2SizeReduction.cpp | 758 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
761 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
793 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
794 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.h | 105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| H A D | MachineInstr.cpp | 2456 Register Reg2 = getOperand(2).getReg(); in getFirst3RegLLTs() local
2458 getRegInfo()->getType(Reg1), Reg2, in getFirst3RegLLTs()
2459 getRegInfo()->getType(Reg2)); in getFirst3RegLLTs()
2466 Register Reg2 = getOperand(2).getReg(); in getFirst4RegLLTs() local
2470 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3)); in getFirst4RegLLTs()
2478 Register Reg2 = getOperand(2).getReg(); in getFirst5RegLLTs() local
2483 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3), in getFirst5RegLLTs()
|
| H A D | TargetInstrInfo.cpp | 187 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
202 Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false; in commuteInstructionImpl()
208 Reg0 = Reg2; in commuteInstructionImpl()
210 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
231 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
244 if (Reg2.isPhysical()) in commuteInstructionImpl()
|
| H A D | AggressiveAntiDepBreaker.cpp | 89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
95 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 270 unsigned Reg2 = in getRegisterSeqOpValue() local
273 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1); in getRegisterSeqOpValue()
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 82 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
83 return contains(Reg1) && contains(Reg2); in contains()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 227 unsigned Reg2, SMLoc IDLoc, in emitRRR() argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
233 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
239 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCDwarf.cpp | 1329 unsigned Reg2 = Instr.getRegister2(); in emitCFIInstruction() local
1332 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); in emitCFIInstruction()
1336 Streamer.emitULEB128IntValue(Reg2); in emitCFIInstruction()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 383 MCRegister Reg2; member
1069 OS << " Reg2 " << RegName(RegReg.Reg2); in print()
1158 Op->RegReg.Reg2 = Reg2No; in createRegReg()
1242 Inst.addOperand(MCOperand::createReg(RegReg.Reg2)); in addRegRegOperands()
2476 MCRegister Reg2 = matchRegisterNameHelper(isRVE(), Reg2Name); in parseRegReg() local
2477 if (!Reg2) in parseRegReg()
2484 Operands.push_back(RISCVOperand::createRegReg(Reg, Reg2, getLoc())); in parseRegReg()
|