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Searched refs:Reduction (Results 1 – 25 of 40) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandVectorPredication.cpp427 Reduction = Builder.CreateAdd(Reduction, Start); in expandPredicationInReduction()
431 Reduction = Builder.CreateMul(Reduction, Start); in expandPredicationInReduction()
435 Reduction = Builder.CreateAnd(Reduction, Start); in expandPredicationInReduction()
439 Reduction = Builder.CreateOr(Reduction, Start); in expandPredicationInReduction()
443 Reduction = Builder.CreateXor(Reduction, Start); in expandPredicationInReduction()
447 Reduction = in expandPredicationInReduction()
452 Reduction = in expandPredicationInReduction()
457 Reduction = in expandPredicationInReduction()
462 Reduction = in expandPredicationInReduction()
468 Reduction = in expandPredicationInReduction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp54 class Reduction;
84 class Reduction { class
92 Reduction() = delete;
94 Reduction (Instruction *Add) : Root(Add) { } in Reduction() function in __anonb3a2f3ff0111::Reduction
220 bool Search(Value *V, BasicBlock *BB, Reduction &R);
222 void InsertParallelMACs(Reduction &Reduction);
225 bool CreateParallelPairs(Reduction &R);
426 bool ARMParallelDSP::Search(Value *V, BasicBlock *BB, Reduction &R) { in Search()
523 Reduction R(&I); in MatchSMLAD()
543 bool ARMParallelDSP::CreateParallelPairs(Reduction &R) { in CreateParallelPairs()
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/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A DOpenACCKinds.h217 Reduction, enumerator
333 case OpenACCClauseKind::Reduction:
H A Darm_mve.td539 multiclass Reduction<Type Accumulator, string basename, list<Type> basetypes,
561 defm vminvq: Reduction<Scalar, "minv", [Vector], 1, (seq (Scalar $ret))>;
562 defm vmaxvq: Reduction<Scalar, "maxv", [Vector], 1, (seq (Scalar $ret))>;
566 defm vminavq: Reduction<UScalar, "minav", [Vector], 0, (seq (UScalar $ret))>;
567 defm vmaxavq: Reduction<UScalar, "maxav", [Vector], 0, (seq (UScalar $ret))>;
571 defm vminnmvq: Reduction<Scalar, "minnmv", [Scalar, Vector]>;
572 defm vmaxnmvq: Reduction<Scalar, "maxnmv", [Scalar, Vector]>;
573 defm vminnmavq: Reduction<Scalar, "minnmav", [Scalar, Vector]>;
574 defm vmaxnmavq: Reduction<Scalar, "maxnmav", [Scalar, Vector]>;
H A Driscv_vector.td2021 // 14. Vector Reduction Operations
2022 // 14.1. Vector Single-Width Integer Reduction Instructions
2035 // 14.2. Vector Widening Integer Reduction Instructions
2036 // Vector Widening Integer Reduction Operations
2044 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2090 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2094 // 14.4. Vector Widening Floating-Point Reduction Instructions
2098 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2102 // 14.4. Vector Widening Floating-Point Reduction Instructions
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp1173 return (all_of(getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeFPMath() argument
1174 const RecurrenceDescriptor &RdxDesc = Reduction.second; in canVectorizeFPMath()
1180 return any_of(getReductionVars(), [&](auto &Reduction) -> bool { in isInvariantStoreOfReduction() argument
1181 const RecurrenceDescriptor &RdxDesc = Reduction.second; in isInvariantStoreOfReduction()
1187 return any_of(getReductionVars(), [&](auto &Reduction) -> bool { in isInvariantAddressOfReduction() argument
1188 const RecurrenceDescriptor &RdxDesc = Reduction.second; in isInvariantAddressOfReduction()
1534 for (const auto &Reduction : getReductionVars()) in prepareToFoldTailByMasking() local
1535 ReductionLiveOuts.insert(Reduction.second.getLoopExitInstr()); in prepareToFoldTailByMasking()
H A DLoopVectorize.cpp1525 return (all_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeReductions() argument
1526 const RecurrenceDescriptor &RdxDesc = Reduction.second; in canVectorizeReductions()
5538 any_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in selectInterleaveCount() argument
5539 const RecurrenceDescriptor &RdxDesc = Reduction.second; in selectInterleaveCount()
5555 any_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in selectInterleaveCount() argument
5556 const RecurrenceDescriptor &RdxDesc = Reduction.second; in selectInterleaveCount()
7215 for (const auto &Reduction : Legal->getReductionVars()) { in collectValuesToIgnore() local
7216 const RecurrenceDescriptor &RedDes = Reduction.second; in collectValuesToIgnore()
7230 for (const auto &Reduction : Legal->getReductionVars()) { in collectInLoopReductions() local
7231 PHINode *Phi = Reduction.first; in collectInLoopReductions()
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/freebsd-14.2/sys/contrib/device-tree/Bindings/power/avs/
H A Dqcom,cpr.txt1 QCOM CPR (Core Power Reduction)
3 CPR (Core Power Reduction) is a technology to reduce core power on a CPU
H A Dqcom,cpr.yaml7 title: Qualcomm Core Power Reduction (CPR)
13 CPR (Core Power Reduction) is a technology to reduce core power on a CPU
/freebsd-14.2/usr.sbin/lpr/filters.ru/
H A Dbjc-240.sh.sample55 Reduction=Off
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVScheduleV.td20 // Used for widening floating-point Reduction as it doesn't contain MF8.
446 // 14. Vector Reduction Operations
451 // 14.1. Vector Single-Width Integer Reduction Instructions
454 // 14.2. Vector Widening Integer Reduction Instructions
460 // 14.4. Vector Widening Floating-Point Reduction Instructions
672 // 14. Vector Reduction Operations
673 // 14.1. Vector Single-Width Integer Reduction Instructions
676 // 14.2. Vector Widening Integer Reduction Instructions
685 // 14.4. Vector Widening Floating-Point Reduction Instructions
900 // 14. Vector Reduction Operations
[all …]
H A DRISCVInstrInfoV.td1512 // Vector Single-Width Integer Reduction Instructions
1524 // Vector Widening Integer Reduction Instructions
1537 // Vector Single-Width Floating-Point Reduction Instructions
1552 // Vector Widening Floating-Point Reduction Instructions
H A DRISCVInstrInfoVPseudos.td179 // For widening floating-point Reduction as it doesn't contain MF8. It can
6646 // 14. Vector Reduction Operations
6651 // 14.1. Vector Single-Width Integer Reduction Instructions
6663 // 14.2. Vector Widening Integer Reduction Instructions
6673 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
6686 // 14.4. Vector Widening Floating-Point Reduction Instructions
7306 // 14. Vector Reduction Operations
7310 // 14.1. Vector Single-Width Integer Reduction Instructions
7322 // 14.2. Vector Widening Integer Reduction Instructions
7328 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dti,cdce925.yaml13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
/freebsd-14.2/contrib/llvm-project/clang/lib/Parse/
H A DParseOpenACC.cpp123 .Case("reduction", OpenACCClauseKind::Reduction) in getOpenACCClauseKind()
485 case OpenACCClauseKind::Reduction: in getClauseParensKind()
693 case OpenACCClauseKind::Reduction: in ParseOpenACCClauseParams()
/freebsd-14.2/sys/contrib/device-tree/Bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml14 voltage is dynamically configured by Core Power Reduction (CPR) depending on
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/TraceExporter/docs/
H A Dhtr.rst33 **Basic Super Block Reduction**
/freebsd-14.2/sys/contrib/device-tree/Bindings/display/msm/
H A Dgpu.yaml153 description: GPU RB Core Power Reduction clock
/freebsd-14.2/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm660-xiaomi-lavender.dts227 * by the Core Power Reduction hardened (CPRh) and the
H A Dsdm670-google-sargo.dts202 * by the Core Power Reduction hardened (CPRh) and the
H A Dsdm630-sony-xperia-nile.dtsi420 * by the Core Power Reduction hardened (CPRh) and the
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td950 // Reduction, arithmetic, B form
953 // Reduction, arithmetic, H form
956 // Reduction, arithmetic, S form
959 // Reduction, arithmetic, D form
962 // Reduction, logical
H A DAArch64SchedNeoverseV1.td1508 // Reduction, arithmetic, B form
1512 // Reduction, arithmetic, H form
1516 // Reduction, arithmetic, S form
1520 // Reduction, arithmetic, D form
1524 // Reduction, logical
H A DAArch64SchedNeoverseN2.td1869 // Reduction, arithmetic, B form
1872 // Reduction, arithmetic, H form
1875 // Reduction, arithmetic, S form
1878 // Reduction, arithmetic, D form
1881 // Reduction, logical
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td842 // For Reduction ternary operations.
852 // For Reduction ternary operations with mask.
863 // For Reduction ternary operations.
873 // For Reduction ternary operations with mask.

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