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Searched refs:ReadAdvance (Results 1 – 25 of 66) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP400.td248 def : ReadAdvance<ReadJmp, 0>;
249 def : ReadAdvance<ReadJalr, 0>;
250 def : ReadAdvance<ReadCSR, 0>;
253 def : ReadAdvance<ReadIALU, 0>;
259 def : ReadAdvance<ReadIDiv, 0>;
261 def : ReadAdvance<ReadIMul, 0>;
333 def : ReadAdvance<ReadCLZ, 0>;
335 def : ReadAdvance<ReadCTZ, 0>;
337 def : ReadAdvance<ReadCPOP, 0>;
339 def : ReadAdvance<ReadORCB, 0>;
[all …]
H A DRISCVSchedSyntacoreSCR1.td137 def : ReadAdvance<ReadJmp, 0>;
138 def : ReadAdvance<ReadJalr, 0>;
139 def : ReadAdvance<ReadCSR, 0>;
142 def : ReadAdvance<ReadIALU, 0>;
143 def : ReadAdvance<ReadIALU32, 0>;
148 def : ReadAdvance<ReadIDiv, 0>;
149 def : ReadAdvance<ReadIDiv32, 0>;
150 def : ReadAdvance<ReadIMul, 0>;
151 def : ReadAdvance<ReadIMul32, 0>;
166 def : ReadAdvance<ReadFMA32, 0>;
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H A DRISCVSchedRocket.td179 def : ReadAdvance<ReadJmp, 0>;
180 def : ReadAdvance<ReadJalr, 0>;
181 def : ReadAdvance<ReadCSR, 0>;
184 def : ReadAdvance<ReadIALU, 0>;
185 def : ReadAdvance<ReadIALU32, 0>;
190 def : ReadAdvance<ReadIDiv, 0>;
191 def : ReadAdvance<ReadIDiv32, 0>;
192 def : ReadAdvance<ReadIMul, 0>;
193 def : ReadAdvance<ReadIMul32, 0>;
208 def : ReadAdvance<ReadFMA32, 0>;
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H A DRISCVScheduleZb.td114 def : ReadAdvance<ReadCLZ, 0>;
115 def : ReadAdvance<ReadCLZ32, 0>;
116 def : ReadAdvance<ReadCTZ, 0>;
117 def : ReadAdvance<ReadCTZ32, 0>;
118 def : ReadAdvance<ReadCPOP, 0>;
120 def : ReadAdvance<ReadREV8, 0>;
121 def : ReadAdvance<ReadORCB, 0>;
129 def : ReadAdvance<ReadCLMUL, 0>;
152 def : ReadAdvance<ReadBREV8, 0>;
153 def : ReadAdvance<ReadPACK, 0>;
[all …]
H A DRISCVSchedSiFive7.td937 def : ReadAdvance<ReadCSR, 0>;
946 def : ReadAdvance<ReadIDiv, 0>;
948 def : ReadAdvance<ReadIMul, 0>;
964 def : ReadAdvance<ReadFMA16, 0>;
968 def : ReadAdvance<ReadFMA32, 0>;
970 def : ReadAdvance<ReadFMA64, 0>;
1027 def : ReadAdvance<ReadCPOP, 0>;
1042 def : ReadAdvance<ReadVLDX, 0>;
1043 def : ReadAdvance<ReadVSTX, 0>;
1046 def : ReadAdvance<ReadVLDSX, 0>;
[all …]
H A DRISCVSchedule.td228 def : ReadAdvance<ReadFAdd16, 0>;
229 def : ReadAdvance<ReadFClass16, 0>;
238 def : ReadAdvance<ReadFDiv16, 0>;
239 def : ReadAdvance<ReadFCmp16, 0>;
240 def : ReadAdvance<ReadFMA16, 0>;
241 def : ReadAdvance<ReadFMinMax16, 0>;
242 def : ReadAdvance<ReadFMul16, 0>;
245 def : ReadAdvance<ReadFSGNJ16, 0>;
246 def : ReadAdvance<ReadFSqrt16, 0>;
254 def : ReadAdvance<ReadSFBJmp, 0>;
[all …]
H A DRISCVScheduleV.td191 // by the ReadAdvance. For example:
939 def : ReadAdvance<ReadVSETVL, 0>;
942 def : ReadAdvance<ReadVLDX, 0>;
943 def : ReadAdvance<ReadVSTX, 0>;
946 def : ReadAdvance<ReadVLDSX, 0>;
947 def : ReadAdvance<ReadVSTSX, 0>;
973 def : ReadAdvance<ReadVST1R, 0>;
974 def : ReadAdvance<ReadVST2R, 0>;
975 def : ReadAdvance<ReadVST4R, 0>;
976 def : ReadAdvance<ReadVST8R, 0>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td106 // These ReadAdvance entries are not used in the Falkor sched model.
107 def : ReadAdvance<ReadI, 0>;
108 def : ReadAdvance<ReadISReg, 0>;
109 def : ReadAdvance<ReadIEReg, 0>;
110 def : ReadAdvance<ReadIM, 0>;
111 def : ReadAdvance<ReadIMA, 0>;
112 def : ReadAdvance<ReadID, 0>;
113 def : ReadAdvance<ReadExtrHi, 0>;
114 def : ReadAdvance<ReadAdrBase, 0>;
115 def : ReadAdvance<ReadVLD, 0>;
[all …]
H A DAArch64SchedKryo.td113 def : ReadAdvance<ReadI, 0>;
114 def : ReadAdvance<ReadISReg, 0>;
115 def : ReadAdvance<ReadIEReg, 0>;
116 def : ReadAdvance<ReadIM, 0>;
117 def : ReadAdvance<ReadIMA, 0>;
118 def : ReadAdvance<ReadID, 0>;
119 def : ReadAdvance<ReadExtrHi, 0>;
120 def : ReadAdvance<ReadAdrBase, 0>;
121 def : ReadAdvance<ReadVLD, 0>;
122 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedThunderX.td194 def : ReadAdvance<ReadExtrHi, 1>;
195 def : ReadAdvance<ReadAdrBase, 2>;
196 def : ReadAdvance<ReadVLD, 2>;
197 def : ReadAdvance<ReadST, 2>;
203 // ReadAdvance applies to Extended registers as well, even though there is
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
229 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
239 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td152 def : ReadAdvance<ReadExtrHi, 0>;
153 def : ReadAdvance<ReadAdrBase, 0>;
154 def : ReadAdvance<ReadST, 0>;
155 def : ReadAdvance<ReadVLD, 0>;
160 // ReadAdvance applies to Extended registers as well, even though there is
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
196 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedA55.td210 def : ReadAdvance<ReadVLD, 0>;
211 def : ReadAdvance<ReadExtrHi, 1>;
212 def : ReadAdvance<ReadAdrBase, 1>;
213 def : ReadAdvance<ReadST, 1>;
219 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
243 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
247 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
253 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedExynosM3.td272 def : ReadAdvance<ReadI, 0>;
273 def : ReadAdvance<ReadISReg, 0>;
274 def : ReadAdvance<ReadIEReg, 0>;
275 def : ReadAdvance<ReadIM, 0>;
277 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
278 def : ReadAdvance<ReadID, 0>;
279 def : ReadAdvance<ReadExtrHi, 0>;
280 def : ReadAdvance<ReadAdrBase, 0>;
281 def : ReadAdvance<ReadVLD, 0>;
282 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedTSV110.td113 def : ReadAdvance<ReadI, 0>;
114 def : ReadAdvance<ReadISReg, 0>;
115 def : ReadAdvance<ReadIEReg, 0>;
116 def : ReadAdvance<ReadIM, 0>;
117 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
118 def : ReadAdvance<ReadID, 0>;
119 def : ReadAdvance<ReadExtrHi, 0>;
120 def : ReadAdvance<ReadAdrBase, 0>;
121 def : ReadAdvance<ReadVLD, 0>;
122 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedCyclone.td187 def : ReadAdvance<ReadExtrHi, 1>;
262 def : ReadAdvance<ReadST, 0>;
638 def : ReadAdvance<ReadVLD, 5>;
868 def : ReadAdvance<ReadI, 0>;
869 def : ReadAdvance<ReadISReg, 0>;
870 def : ReadAdvance<ReadIEReg, 0>;
871 def : ReadAdvance<ReadIM, 0>;
872 def : ReadAdvance<ReadIMA, 0>;
873 def : ReadAdvance<ReadID, 0>;
H A DAArch64SchedA57.td114 def : ReadAdvance<ReadI, 0>;
115 def : ReadAdvance<ReadISReg, 0>;
116 def : ReadAdvance<ReadIEReg, 0>;
117 def : ReadAdvance<ReadIM, 0>;
118 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
119 def : ReadAdvance<ReadID, 0>;
120 def : ReadAdvance<ReadExtrHi, 0>;
121 def : ReadAdvance<ReadST, 0>;
122 def : ReadAdvance<ReadAdrBase, 0>;
123 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedAmpere1.td675 def : ReadAdvance<ReadI, 0>;
676 def : ReadAdvance<ReadISReg, 0>;
677 def : ReadAdvance<ReadIEReg, 0>;
678 def : ReadAdvance<ReadIM, 0>;
679 def : ReadAdvance<ReadIMA, 1, [WriteIM32, WriteIM64]>;
680 def : ReadAdvance<ReadID, 0>;
681 def : ReadAdvance<ReadExtrHi, 0>;
682 def : ReadAdvance<ReadST, 0>;
683 def : ReadAdvance<ReadAdrBase, 0>;
684 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedAmpere1B.td631 def : ReadAdvance<ReadI, 0>;
632 def : ReadAdvance<ReadISReg, 0>;
633 def : ReadAdvance<ReadIEReg, 0>;
634 def : ReadAdvance<ReadIM, 0>;
635 def : ReadAdvance<ReadIMA, 1, [WriteIM32, WriteIM64]>;
636 def : ReadAdvance<ReadID, 0>;
637 def : ReadAdvance<ReadExtrHi, 0>;
638 def : ReadAdvance<ReadST, 0>;
639 def : ReadAdvance<ReadAdrBase, 0>;
640 def : ReadAdvance<ReadVLD, 0>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp524 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
525 if (ReadAdvance < 0) { in collectWrites()
527 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
540 if (ReadAdvance < 0) { in collectWrites()
542 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
582 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in checkRAWHazards() local
593 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRAWHazards()
643 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in addRegisterRead() local
644 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()
651 unsigned ReadAdvance = static_cast<unsigned>( in addRegisterRead() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td100 def : ReadAdvance<ReadALU, 0>;
101 def : ReadAdvance<ReadALUsr, 0>;
102 def : ReadAdvance<ReadMUL, 0>;
103 def : ReadAdvance<ReadMAC, 0>;
134 def : ReadAdvance<ReadFPMUL, 0>;
135 def : ReadAdvance<ReadFPMAC, 0>;
H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
175 def : ReadAdvance<ReadALUsr, 0>;
176 def : ReadAdvance<ReadMUL, 0>;
177 def : ReadAdvance<ReadMAC, 1>;
178 def : ReadAdvance<ReadALU, 0>;
179 def : ReadAdvance<ReadFPMUL, 0>;
180 def : ReadAdvance<ReadFPMAC, 3>;
H A DARMScheduleR52.td87 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
89 def : ReadAdvance<ReadMUL, 0>;
90 def : ReadAdvance<ReadMAC, 0>;
127 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
128 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
134 def : ReadAdvance<R52Read_ISS, 0>;
135 def : ReadAdvance<R52Read_EX1, 1>;
136 def : ReadAdvance<R52Read_EX2, 2>;
137 def : ReadAdvance<R52Read_F0, 0>;
138 def : ReadAdvance<R52Read_F1, 1>;
[all …]
H A DARMScheduleM55.td239 def : ReadAdvance<ReadALU, 0>;
240 def : ReadAdvance<ReadALUsr, 0>;
241 def : ReadAdvance<ReadMUL, 0>;
242 def : ReadAdvance<ReadMAC, 0>;
443 def : ReadAdvance<ReadFPMUL, 0>;
444 def : ReadAdvance<ReadFPMAC, 0>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp72 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { in addUser() argument
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
82 Users.emplace_back(User, ReadAdvance); in addUser()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td50 def : ReadAdvance<ReadAfterLd, 3>;
51 def : ReadAdvance<ReadAfterVecLd, 3>;
52 def : ReadAdvance<ReadAfterVecXLd, 3>;
53 def : ReadAdvance<ReadAfterVecYLd, 3>;
55 def : ReadAdvance<ReadInt2Fpu, 0>;

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