Searched refs:RdLo (Results 1 – 5 of 5) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 4305 bits<4> RdLo;
4310 let Inst{15-12} = RdLo;
4317 bits<4> RdLo;
4322 let Inst{15-12} = RdLo;
4391 [(set GPR:$RdLo, GPR:$RdHi,
4443 bits<4> RdLo;
4448 let Inst{15-12} = RdLo;
4454 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4614 (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4670 bits<4> RdLo;
[all …]
|
| H A D | ARMInstrThumb2.td | 687 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
688 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
690 bits<4> RdLo;
698 let Inst{15-12} = RdLo;
704 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
706 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
707 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
709 bits<4> RdLo;
717 let Inst{15-12} = RdLo;
3076 [(set rGPR:$RdLo, rGPR:$RdHi,
[all …]
|
| H A D | ARMInstrFormats.td | 1016 bits<4> RdLo;
1019 let Inst{15-12} = RdLo;
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrAtomics.td | 513 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch",
515 class cmp_swap_128 : Pseudo<(outs GPR64common:$RdLo, GPR64common:$RdHi,
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 8346 unsigned RdLo = Inst.getOperand(1).getReg(); in validateInstruction() local
8347 if(RdHi == RdLo) { in validateInstruction()
|