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Searched refs:Ra (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp159 unsigned Ra) { in addIntraChainConstraint() argument
160 if (Rd == Ra) in addIntraChainConstraint()
169 << Register::isPhysicalRegister(Ra) << '\n'); in addIntraChainConstraint()
187 const LiveInterval &la = LIs.getInterval(Ra); in addIntraChainConstraint()
243 unsigned Ra) { in addInterChainConstraint() argument
247 if (Chains.count(Ra)) { in addInterChainConstraint()
248 if (Rd != Ra) { in addInterChainConstraint()
251 Chains.remove(Ra); in addInterChainConstraint()
363 Register Ra = MI.getOperand(3).getReg(); in apply() local
365 if (addIntraChainConstraint(G, Rd, Ra)) in apply()
[all …]
H A DAArch64PBQPRegAlloc.h32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64InstrInfo.td2182 GPR64:$Ra)),
4762 def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, FPR16:$Ra)),
4763 (FMSUBHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;
4766 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
4769 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
4775 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;
4778 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
4781 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5876 V64:$Ra,
5884 V64:$Ra,
[all …]
H A DAArch64InstrFormats.td2607 bits<5> Ra;
2612 let Inst{14-10} = Ra;
2633 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
5489 bits<5> Ra;
5494 let Inst{14-10} = Ra;
5523 (f16 FPR16:$Ra))),
5529 (f16 FPR16:$Ra))),
5536 (f32 FPR32:$Ra))),
5542 (f32 FPR32:$Ra))),
5548 (f64 FPR64:$Ra))),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp125 MCRegister Ra; in expandFunctionCall() local
128 Ra = RISCV::X6; in expandFunctionCall()
131 Ra = MI.getOperand(0).getReg(); in expandFunctionCall()
134 Ra = RISCV::X1; in expandFunctionCall()
137 Ra = MI.getOperand(0).getReg(); in expandFunctionCall()
146 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); in expandFunctionCall()
153 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
156 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() local
93 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(ARC::FLS_f_rr), Ra) in expandCTLZ()
98 .addReg(Ra); in expandCTLZ()
/freebsd-14.2/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2621 pxor $Ra, $Ra
2648 por $T0a, $Ra
2741 pxor $Ra, $Ra
2833 vpxor $Ra, $Ra, $Ra
2868 vpxor $T0a, $Ra, $Ra
2871 vpxor $T1a, $Ra, $Ra
2941 vpxor $Ra, $Ra, $Ra
2980 vpxor $T0a, $Ra, $Ra
2982 vpxor $T1a, $Ra, $Ra
2984 vpxor $T2a, $Ra, $Ra
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td4070 "\t$Rd, $Rn, $Rm, $Ra",
4076 bits<4> Ra;
4080 let Inst{15-12} = Ra;
4357 bits<4> Ra;
4358 let Inst{15-12} = Ra;
4378 bits<4> Ra;
4380 let Inst{15-12} = Ra;
4561 [(set GPRnopc:$Rd, (add GPR:$Ra,
4585 [(set GPRnopc:$Rd, (add GPR:$Ra,
4662 bits<4> Ra;
[all …]
H A DARMInstrThumb2.td677 bits<4> Ra;
680 let Inst{15-12} = Ra;
2691 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
3050 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3056 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3113 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3180 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3269 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
3281 (outs rGPR:$Ra, rGPR:$Rd),
5800 bits<4> Ra;
[all …]
H A DARMInstrFormats.td975 // MSW multiple w/ Ra operand
979 bits<4> Ra;
980 let Inst{15-12} = Ra;
1005 // AMulxyI with Ra operand
1009 bits<4> Ra;
1010 let Inst{15-12} = Ra;
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltins.def623 BUILTIN(__builtin_vprintf, "icC*Ra", "nFP:0:")
624 BUILTIN(__builtin_vfprintf, "iP*RcC*Ra", "nFP:1:")
625 BUILTIN(__builtin_vsprintf, "ic*RcC*Ra", "nFP:1:")
626 BUILTIN(__builtin_vsnprintf, "ic*RzcC*Ra", "nFP:2:")
630 BUILTIN(__builtin_vfscanf, "iP*RcC*Ra", "FS:1:")
631 BUILTIN(__builtin_vscanf, "icC*Ra", "FS:0:")
632 BUILTIN(__builtin_vsscanf, "icC*RcC*Ra", "FS:1:")
663 BUILTIN(__builtin___vsnprintf_chk, "ic*RzizcC*Ra", "FP:4:")
664 BUILTIN(__builtin___vsprintf_chk, "ic*RizcC*Ra", "FP:3:")
667 BUILTIN(__builtin___vfprintf_chk, "iP*RicC*Ra", "FP:2:")
[all …]
/freebsd-14.2/tools/regression/iscsi/
H A Discsi-test.sh152 check iscsictl -Ra
764 check iscsictl -Ra
/freebsd-14.2/contrib/tzdata/
H A Dsouthamerica1729 # From Carlos Raúl Perasso via Jesper Nørgaard Welen (2006-10-13)
1733 # From Carlos Raúl Perasso (2010-02-18):
1751 # From Carlos Raúl Perasso (2013-03-15):
1754 # From Carlos Raúl Perasso (2014-02-28):
1761 # From Carlos Raúl Perasso (2023-07-27):
H A DNEWS3372 (Thanks to Carlos Raúl Perasso.)
4097 Paraguay's 2014 DST will be as predicted. (Thanks to Carlos Raúl Perasso.)
4582 (Thanks to Carlos Raúl Perasso.)
H A Dnorthamerica2614 # From Carlos Raúl Perasso (2015-02-02):
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td955 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
956 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
957 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
958 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2741 unsigned Ra = fieldFromInstruction(Insn, 12, 4); in DecodeSMLAInstruction() local
2753 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) in DecodeSMLAInstruction()
/freebsd-14.2/contrib/tzcode/
H A DNEWS3269 (Thanks to Carlos Raúl Perasso.)
3994 Paraguay's 2014 DST will be as predicted. (Thanks to Carlos Raúl Perasso.)
4479 (Thanks to Carlos Raúl Perasso.)
/freebsd-14.2/contrib/sendmail/
H A DPGPKEYS111 V9xOCqCWvcJ8gC+Ra+h5PN+ESy4Qqo771fNThV4C5QMQ6t8I+JPiepI+H4U19zxb