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Searched refs:RVV (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp270 const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr; in getSchedClassID() local
274 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW); in getSchedClassID()
277 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW); in getSchedClassID()
279 if (!RVV) in getSchedClassID()
280 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0); in getSchedClassID()
284 if (!RVV) { in getSchedClassID()
300 << " with " << MCII.getName(RVV->Pseudo) << '\n'); in getSchedClassID()
301 return MCII.get(RVV->Pseudo).getSchedClass(); in getSchedClassID()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Sema/
H A DRISCVIntrinsicManager.h27 enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR }; enumerator
/freebsd-14.2/contrib/llvm-project/clang/lib/Sema/
H A DSemaRISCVVectorLookup.cpp79 case IntrinsicKind::RVV: in ProtoSeq2ArrayRef()
352 IntrinsicKind::RVV); in InitIntrinsicList()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVAsmPrinter.cpp879 const RISCVVPseudosTable::PseudoInfo *RVV = in lowerRISCVVMachineInstrToMCInst() local
881 if (!RVV) in lowerRISCVVMachineInstrToMCInst()
884 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
H A DRISCVInstrInfo.cpp3403 const RISCVVPseudosTable::PseudoInfo *RVV = in getRVVMCOpcode() local
3405 if (!RVV) in getRVVMCOpcode()
3407 return RVV->BaseInstr; in getRVVMCOpcode()
H A DRISCVInstrInfoVSDPatterns.td1 //===- RISCVInstrInfoVSDPatterns.td - RVV SDNode patterns --*- tablegen -*-===//
15 /// Note: the patterns for RVV intrinsics are found in
H A DRISCVInstrInfoVVLPatterns.td1 //===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===//
15 /// Note: the patterns for RVV intrinsics are found in
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector_common.td9 // This file defines RVV builtin base class for RISC-V V-extension.
73 // will yield an RVV vector type (assume LMUL=1), so __rvv_int32m1_t.
H A DDiagnosticSemaKinds.td3182 "invalid RVV vector size '%0', expected size is '%1' based on LMUL of type "
3185 "%0 attribute applied to non-RVV type %1">;
3301 "cannot combine fixed-length and sizeless %select{SVE|RVV}0 vectors "
3304 …"cannot combine GNU and %select{SVE|RVV}0 vectors in expression, result is ambiguous (%1 and %2)">;
H A DAttrDocs.td2418 The attribute can be attached to a single RVV vector (such as ``vint8m1_t``).
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Driver/
H A DOptions.td4619 HelpText<"Specify the size in bits of an RVV vector register">,