Searched refs:RV64 (Results 1 – 12 of 12) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | EmulateInstructionRISCV.cpp | 510 {"C_LDSP", 0xE003, 0x6002, DecodeC_LDSP, RV64 | RV128}, 512 {"C_SDSP", 0xE003, 0xE002, DecodeC_SDSP, RV64 | RV128}, 514 {"C_LD", 0xE003, 0x6000, DecodeC_LD, RV64 | RV128}, 516 {"C_SD", 0xE003, 0xE000, DecodeC_SD, RV64 | RV128}, 527 {"C_SLLI", 0xE003, 0x2, DecodeC_SLLI, RV64 | RV128}, 528 {"C_SRLI", 0xEC03, 0x8001, DecodeC_SRLI, RV64 | RV128}, 545 {"FLDSP", 0xE003, 0x2002, DecodeC_FLDSP, RV32 | RV64}, 546 {"FSDSP", 0xE003, 0xA002, DecodeC_FSDSP, RV32 | RV64}, 547 {"FLD", 0xE003, 0x2000, DecodeC_FLD, RV32 | RV64}, 548 {"FSD", 0xE003, 0xA000, DecodeC_FSD, RV32 | RV64}, [all …]
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| H A D | RISCVInstructions.h | 294 constexpr uint8_t RV64 = 2; variable 305 uint8_t inst_type = RV32 | RV64 | RV128;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.td | 119 def XLenVT : ValueTypeByHwMode<[RV32, RV64], 121 // Allow f64 in GPR for ZDINX on RV64. 122 def XLenFVT : ValueTypeByHwMode<[RV64], 127 [RV32, RV64], 575 let RegInfos = RegInfoByHwMode<[RV32, RV64],
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| H A D | RISCVInstrInfoM.td | 119 // Experimental RV64 i32 legalization patterns.
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| H A D | RISCVFeatures.td | 989 : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">; 998 def RV64 : HwMode<"+64bit", [IsRV64]>;
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| H A D | RISCVInstrInfoA.td | 372 // Experimental RV64 i32 legalization patterns.
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| H A D | RISCVInstrInfoXTHead.td | 676 // mulaw, mulsw are available only in RV64. 902 // Experimental RV64 i32 legalization patterns.
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| H A D | RISCVInstrInfo.td | 1908 /// RV64 patterns 2011 // On RV64, we can directly read the 64-bit "cycle" CSR. 2067 // Experimental RV64 i32 legalization patterns.
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| H A D | RISCVInstrInfoZb.td | 823 // Experimental RV64 i32 legalization patterns.
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| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | riscv_sifive_vector.td | 52 ["Xsfvcp", "RV64"], ["Xsfvcp"]) in 60 ["Xsfvcp", "RV64"], ["Xsfvcp"]) in
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| H A D | riscv_vector.td | 131 RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], 132 ["RV64"]) in { 236 RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], 237 ["RV64"]) in {
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| H A D | DiagnosticDriverKinds.td | 585 "ignoring '-msmall-data-limit=' with -mcmodel=large for -fpic or RV64">,
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