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Searched refs:RMII (Results 1 – 25 of 42) sorted by relevance

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/freebsd-14.2/sys/contrib/device-tree/Bindings/net/
H A Dmediatek-dwmac.yaml54 - description: RMII reference clock provided by MAC
81 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
91 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
99 If present, indicates that the RMII reference clock, which is from external
105 If present, indicates that MAC provides the RMII reference clock, which
114 which is from external PHYs in RMII case, and it rarely happen.
115 3. the reference clock, which outputs to TXC pin will be inversed in RMII case
123 2. reference clock will be inversed when arrived at MAC in RMII case, when
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H A Dmediatek-dwmac.txt26 It should be defined for RMII interface when the reference clock is from MT2712 SoC.
29 It should be defined for RMII interface.
32 Both delay properties need to be a multiple of 550 for MII/RMII interface,
35 - mediatek,rmii-rxc: boolean property, if present indicates that the RMII
40 MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
44 which is from external PHYs in RMII case, and it rarely happen.
45 3. the reference clock, which outputs to TXC pin will be inversed in RMII case
49 2. reference clock will be inversed when arrived at MAC in RMII case, when
51 3. the inside clock, which be sent to MAC, will be inversed in RMII case when
H A Dnxp,tja11xx.yaml38 in RMII mode. This clock signal is provided by the PHY and is
45 interface reference clock input when RMII mode enabled.
47 reference clock output when RMII mode enabled.
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
H A Drockchip-dwmac.txt24 <&cru SCLK_MACREF>: clock gate for RMII referce clock
25 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
33 is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
H A Dftgmac100.txt29 IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
34 - "RCLK": Clock gate for the RMII RCLK
H A Dcpsw-phy-sel.txt13 -rmii-clock-ext : If present, the driver will configure the RMII
H A Dvertexcom-mse102x.yaml14 They can be connected either via RGMII, RMII or SPI to a host CPU.
H A Ddavinci_emac.txt23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
H A Dactions,owl-emac.yaml14 It provides the RMII and SMII interfaces and is compliant with the
H A Dadi,adin.yaml35 When operating in RMII mode, this option configures the FIFO depth.
/freebsd-14.2/sys/contrib/device-tree/src/powerpc/
H A Dkmeter1.dts346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
432 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
437 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
442 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
447 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
452 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
/freebsd-14.2/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy-gmii-sel.txt5 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
21 | | | RMII <------->
47 cell 2 - RMII refclk mode
H A Dti,phy-gmii-sel.yaml15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
31 | | | RMII <------->
154 - RMII refclk mode
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
38 - description: GMAC0 RMII reference
H A Dstarfive,jh7110-syscrg.yaml23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
33 - description: GMAC1 RMII reference
H A Dstarfive,jh7100-clkgen.yaml24 - description: RMII reference clock (50 MHz)
H A Drockchip,rk3188-cru.txt37 - "ext_rmii" - external RMII clock - optional,
H A Drockchip,rk3188-cru.yaml30 - "ext_rmii" - external RMII clock - optional
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dimx53-kp-hsc.dts18 fixed-link { /* RMII fixed link to LAN9303 */
35 port@0 { /* RMII fixed link to master */
H A Dam335x-icev2.dts204 /* Slave 1, RMII mode */
213 /* Slave 2, RMII mode */
471 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/dsa/
H A Dlan9303.txt31 fixed-link { /* RMII fixed link to LAN9303 */
47 port@0 { /* RMII fixed link to master */
H A Darrow,xrs700x.yaml18 RGMII ports and one RMII port and are managed via i2c or mdio.
H A Dsja1105.txt32 - In the case of MII or RMII it specifies whether the SJA1105 port is a
50 ports are at both ends of a MII/RMII PHY-less setup. One end would need
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/pcs/
H A Drenesas,rzn1-miic.yaml14 responsible to do MII passthrough or convert it to RMII/RGMII.
36 - description: RMII reference clock

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