| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSubtarget.cpp | 68 void RISCVSubtarget::anchor() {} in anchor()
70 RISCVSubtarget &
94 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, in RISCVSubtarget() function in RISCVSubtarget
129 bool RISCVSubtarget::useConstantPoolForLargeInts() const { in useConstantPoolForLargeInts()
133 unsigned RISCVSubtarget::getMaxBuildIntsCost() const { in getMaxBuildIntsCost()
144 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const { in getMaxRVVVectorSizeInBits()
157 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { in getMinRVVVectorSizeInBits()
182 bool RISCVSubtarget::useRVVForFixedLengthVectors() const { in useRVVForFixedLengthVectors()
186 bool RISCVSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness()
192 void RISCVSubtarget::getPostRAMutations( in getPostRAMutations()
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| H A D | RISCVTargetMachine.h | 26 mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
35 const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;
39 const RISCVSubtarget *getSubtargetImpl() const = delete;
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| H A D | RISCVMakeCompressible.cpp | 145 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>(); in isCompressibleLoad()
154 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>(); in isCompressibleStore()
323 const RISCVSubtarget &STI = Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVFrameLowering.h | 20 class RISCVSubtarget; variable
24 explicit RISCVFrameLowering(const RISCVSubtarget &STI);
78 const RISCVSubtarget &STI;
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| H A D | RISCVOptWInstrs.cpp | 60 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
62 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
109 const RISCVSubtarget &ST, in hasAllNBitUsers()
333 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers()
384 static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, in isSignExtendedW()
623 const RISCVSubtarget &ST, in removeSExtWInstrs()
675 const RISCVSubtarget &ST, in stripWSuffixes()
708 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVRegisterInfo.cpp | 59 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); in getCalleeSavedRegs()
93 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getReservedRegs()
149 return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg); in isAsmClobberable()
202 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in adjustReg()
283 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>(); in lowerVSPILL()
360 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>(); in lowerVRELOAD()
433 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in eliminateFrameIndex()
679 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getCallPreservedMask()
746 return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 1 : 0; in getRegisterCostTableIndex()
756 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getRegAllocationHints()
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| H A D | RISCV.h | 25 class RISCVSubtarget; variable
86 RISCVSubtarget &,
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| H A D | RISCVExpandAtomicPseudoInsts.cpp | 33 const RISCVSubtarget *STI;
76 STI = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
154 const RISCVSubtarget *Subtarget) { in getLRForRMW32()
176 const RISCVSubtarget *Subtarget) { in getSCForRMW32()
198 const RISCVSubtarget *Subtarget) { in getLRForRMW64()
220 const RISCVSubtarget *Subtarget) { in getSCForRMW64()
242 const RISCVSubtarget *Subtarget) { in getLRForRMW()
251 const RISCVSubtarget *Subtarget) { in getSCForRMW()
264 const RISCVSubtarget *STI) { in doAtomicBinOpExpansion()
328 const RISCVSubtarget *STI) { in doMaskedAtomicBinOpExpansion()
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| H A D | RISCVInsertReadWriteCSR.cpp | 94 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVSubtarget.h | 59 class RISCVSubtarget : public RISCVGenSubtargetInfo {
93 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
101 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
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| H A D | RISCVTargetMachine.cpp | 174 const RISCVSubtarget *
245 I = std::make_unique<RISCVSubtarget>( in getSubtargetImpl()
358 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); in createMachineScheduler()
375 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); in createPostMachineScheduler()
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| H A D | RISCVMachineFunctionInfo.h | 118 MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
139 return MF.getSubtarget<RISCVSubtarget>().hasStdExtZcmp() &&
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| H A D | RISCVCodeGenPrepare.cpp | 38 const RISCVSubtarget *ST;
164 ST = &TM.getSubtarget<RISCVSubtarget>(F); in runOnFunction()
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| H A D | RISCVPushPopOptimizer.cpp | 112 const RISCVSubtarget *Subtarget = &Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVFrameLowering.cpp | 38 RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI) in RISCVFrameLowering()
58 const auto &STI = MF.getSubtarget<RISCVSubtarget>(); in emitSCSPrologue()
115 const auto &STI = MF.getSubtarget<RISCVSubtarget>(); in emitSCSEpilogue()
363 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } in getFPReg()
366 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } in getSPReg()
994 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in determineCalleeSaves()
1050 const auto &ST = MF.getSubtarget<RISCVSubtarget>(); in assignRVVStackObjectOffsets()
1105 if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions()) in getScavSlotsNumForRVV()
1147 return MF.getSubtarget<RISCVSubtarget>().hasVInstructions(); in hasRVVFrameObject()
1175 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtC()) in estimateFunctionSizeInBytes()
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| H A D | RISCVFoldMasks.cpp | 184 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVInstrInfo.h | 26 class RISCVSubtarget; variable
53 explicit RISCVInstrInfo(RISCVSubtarget &STI);
266 const RISCVSubtarget &STI;
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| H A D | RISCVMoveMerger.cpp | 217 const RISCVSubtarget *Subtarget = &Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVExpandPseudoInsts.cpp | 33 const RISCVSubtarget *STI;
70 STI = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
391 const RISCVSubtarget *STI;
445 STI = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
564 const auto &STI = MF->getSubtarget<RISCVSubtarget>(); in expandLoadTLSDescAddress()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 49 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg()
162 const RISCVSubtarget &Subtarget;
187 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg()
278 const RISCVSubtarget &Subtarget;
389 const RISCVSubtarget &Subtarget = in lowerReturnVal()
390 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>(); in lowerReturnVal()
432 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in saveVarArgRegisters()
503 const RISCVSubtarget &Subtarget = in lowerFormalArguments()
504 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>(); in lowerFormalArguments()
554 const RISCVSubtarget &Subtarget = in lowerCall()
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| H A D | RISCVO0PreLegalizerCombiner.cpp | 45 const RISCVSubtarget &STI;
52 const RISCVSubtarget &STI);
72 const RISCVSubtarget &STI) in RISCVO0PreLegalizerCombinerImpl()
130 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVPreLegalizerCombiner.cpp | 47 const RISCVSubtarget &STI;
54 const RISCVSubtarget &STI, MachineDominatorTree *MDT,
75 const RISCVSubtarget &STI, MachineDominatorTree *MDT, in RISCVPreLegalizerCombinerImpl()
138 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVPostLegalizerCombiner.cpp | 52 const RISCVSubtarget &STI;
59 const RISCVSubtarget &STI, MachineDominatorTree *MDT,
80 const RISCVSubtarget &STI, MachineDominatorTree *MDT, in RISCVPostLegalizerCombinerImpl()
142 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
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| H A D | RISCVLegalizerInfo.h | 22 class RISCVSubtarget; variable
25 const RISCVSubtarget &STI;
30 RISCVLegalizerInfo(const RISCVSubtarget &ST);
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| H A D | RISCVRegisterBankInfo.cpp | 312 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
335 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
430 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
441 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD()); in getInstrMapping()
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