Searched refs:RISCVAsmParser (Results 1 – 4 of 4) sorted by relevance
66 class RISCVAsmParser : public MCTargetAsmParser { class632 return RISCVAsmParser::isSymbolDiff(getImm()); in isImmXLenLI()1346 bool RISCVAsmParser::generateImmOutOfRangeError( in generateImmOutOfRangeError()1352 bool RISCVAsmParser::generateImmOutOfRangeError( in generateImmOutOfRangeError()2692 bool RISCVAsmParser::isSymbolDiff(const MCExpr *Expr) { in isSymbolDiff()2760 bool RISCVAsmParser::parseDirectiveOption() { in parseDirectiveOption()2947 bool RISCVAsmParser::parseDirectiveAttribute() { in parseDirectiveAttribute()3032 bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) { in parseDirectiveInsn()3063 bool RISCVAsmParser::parseDirectiveVariantCC() { in parseDirectiveVariantCC()3342 bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst, in checkPseudoAddTPRel()[all …]
62 def RISCVAsmParser : AsmParser {73 let AssemblyParsers = [RISCVAsmParser];
39 // 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number
1533 SRCS_MIN+= Target/RISCV/AsmParser/RISCVAsmParser.cpp