Searched refs:RHSL (Results 1 – 3 of 3) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 3090 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_MINMAX() local
3105 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_MINMAX() local
3131 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_MINMAX() local
3198 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_ADDSUB() local
3203 SDValue LoOps[2] = { LHSL, RHSL }; in ExpandIntRes_ADDSUB()
3339 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_ADDSUBC() local
3365 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_ADDSUBE() local
3412 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_UADDSUBO() local
3456 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_UADDSUBO_CARRY() local
3476 SDValue LHSL, LHSH, RHSL, RHSH; in ExpandIntRes_SADDSUBO_CARRY() local
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 703 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in ExpandADDSUB() local
715 LHSL, RHSL, Zero); in ExpandADDSUB()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1549 Register RHSL = RHSPartRegs[0]; in narrowScalar() local
1555 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); in narrowScalar()
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